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Found 1 result

  1. In our testbench , we have added a new schedule pcie_main_schedule which runs in parallel with uvm_main_phase. This schedule consists of four phase lets say phase_a , phase_b , phase_c and phase_d. So the flow looks as shown below: pre_reset_phase | | <Other run time phase > | | Main_phase | phase_a | | | | | phase_b | | | | | phase_c | | | | | phase_d | / | / | / | / | / | / | / | / | / |/ Post_main_phase When we enter into phase_b , we issue a phase jump to uvm_pre_reset_phase. In this case I see that phase_b is killed and control goes to uvm_pre_reset_phase. But uvm_main_phase keeps on running in parallel.So simulation has both uvm_pre_reset_phase and uvm_main_phase running in parallel which is not expected. As per UVM user guide , if the jump to phase is outside of current schedule then the jump affects other schedules which share this phase. As the jump is happening from phase_b ( part of pcie_main_schedule) to uvm_pre_reset_phase( part of m_uvm_schedule) , uvm_main_phase should also have jumped . But this does not happen.
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