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Found 1 result

  1. Hi all, I met one problem about interface in UVM when i use uvm_config_db; Codes: There is such a line code in duv_pkg.sv typedef virtual duv_sigif duv_vif; There are such codes in duv_tb_top.sv ... duv_sigif fifo_vif[`PORTS_NUM] (clk, rst); // SystemVerilog Interface ... for (int i = 0; i < `PORTS_NUM; i++) begin uvm_config_db#(duv_vif)::set(uvm_root::get(), $sformatf("*.env.subenv[%0d].*", i), "tb_vif", fifo_vif[i]); end ... VCS reports: Error-[iND] Identifier not declared duv_tb_top.sv, 104 Identifier 'fifo_vif' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. If I change the codes above as follows: Codes: There is such a line code in duv_pkg.sv typedef virtual duv_sigif duv_vif; There are such codes in duv_tb_top.sv ... duv_sigif fifo_vif(clk, rst); // SystemVerilog Interface ... //for (int i = 0; i < `PORTS_NUM; i++) begin //uvm_config_db#(duv_vif)::set(uvm_root::get(), $sformatf("*.env.subenv[%0d].*", i), "tb_vif", fifo_vif[i]); uvm_config_db#(duv_vif)::set(uvm_root::get(), "*", "tb_vif", fifo_vif); //end ... The VCS error disappears. Could anybody tell me the reason? By the way, I want to implement multiple interfaces as the duv has multiple ports which are the same.
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