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Showing results for tags 'inheritance'.
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mramdas posted a topic in UVM SystemVerilog DiscussionsIs it possible to do a uvm_config_db::set() for an object of derived class type using the base class handle and later do a uvm_config_db::get() of same object using the derived class handle Since a base class handle can be used to point to a derived class object and later typecase, I thought this would work, but doesn't seem to be so. Any help will be appreciated? Here is an example class BaseA ; endclass class DerivedA extends BaseA endclass 1) Set config_db DerivedA a1; a1 = DerivedA::create() uvm_config_db#(DerivedA)::set(this, "" , "myobj", a1); 2) Get config_db BaseA a1; DerivedA a2; uvm_config_db#(BaseA)::get(this, "" , "myobj", a1); $cast(a2, a1);
ysap posted a topic in SystemC LanguageIs it possible to define a SC class as a derivative of another SC class? For example, a simple D-Flipflop (latch) implementation will have d and clk inputs and a q output. I want to define an Enabled-Latch on top of that class adding the en input and changing the sampling method accordingly. Is this possible? (For reference, question also posted in http://stackoverflow.com/q/37127066/274579but no replies yet)