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shubham_dce posted a topic in UVM Simulator Specific IssuesHi, I am very new to this forum, so please pardon any decorum that i may have violated. Here is the reference code : always @(posedge clk or negedge resetn) begin if(~resetn) begin for(int j=0; j<64; j++) enable_data[j] <= 1'b1; end else begin if(data_accepted) begin: ENABLE_DATA_BLOCK -> event_1; for (int k=0; k<64; k++) begin -> event_2; if (enable_data[k] && queue_pos_available[k]) begin -> event_3; enable_data [k] <=0; -> event_4; disable ENABLE_DATA_BLOCK; end end // for loop end // if(data_accepted) end // else block end // always... While running the above code in incisiv (version incisiv/15.20.016) i am facing the following issue: with all the condition being true that is data_accepted=1, enable_data[k]=1 and queue_pos_available[k]=1 enable_data[k] is not taking the assignment 0. event_3 and event_4 both are triggering. I ran the code by removing disable to break and the code ran correctly. So, i think there is a problem by using disable. I can't go with this fix as break is not synthesisable. My lint-run is not passing with the change of break. Thinking that there is a problem with the use of disable, i tried breaking the loop by setting the loop variable to its maximum value as: . . . if (enable_data[k] && queue_pos_available[k]) begin -> event_3; enable_data [k] <=0; -> event_4; k=64; // i am using blocking statement as i wanted to break the loop immediately. end . . I want to add a point that the code is running fine with VCS and modelsim simulators. If any-one can direct me of what can be the issue here, it will be of real help. Thanks for your time. Regards, Shubham verma