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Found 4 results

  1. Hi , To whom may correspond I think there is some kind of error in the UVM 1.1d register model. I have been experimenting with the UVM register model and i have seen the following code in uvm_reg_map.svh task uvm_reg_map::do_bus_write (uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter); uvm_reg_addr_t addrs[$]; uvm_reg_map system_map = get_root_map(); int unsigned bus_width = get_n_bytes(); uvm_reg_byte_en_t byte_en = -1; uvm_reg_map_info map_info; int n_bits; int lsb; int skip; int unsigned curr_byte; int n_access_extra, n_access; int n_bits_init; Xget_bus_infoX(rw, map_info, n_bits_init, lsb, skip); addrs=map_info.addr; // if a memory, adjust addresses based on offset if (rw.element_kind == UVM_MEM) foreach (addrs[i]) addrs[i] = addrs[i] + map_info.mem_range.stride * rw.offset; foreach (rw.value[val_idx]) begin: foreach_value uvm_reg_data_t value = rw.value[val_idx]; /* calculate byte_enables */ if (rw.element_kind == UVM_FIELD) begin int temp_be; int idx; n_access_extra = lsb%(bus_width*8); n_access = n_access_extra + n_bits_init; temp_be = n_access_extra; value = value << n_access_extra; while(temp_be >= 8) begin byte_en[idx++] = 0; temp_be -= 8; end temp_be += n_bits_init; while(temp_be > 0) begin byte_en[idx++] = 1; temp_be -= 8; end byte_en &= (1<<idx)-1; for (int i=0; i<skip; i++) void'(addrs.pop_front()); while (addrs.size() > (n_bits_init/(bus_width*8) + 1)) void'(addrs.pop_back()); end curr_byte=0; n_bits= n_bits_init; The code continues but the interesting part is already there. Lets assume we have a register with 4 bytes and 1byte per address granularity (byte_addressing). Now, we do a FIELD access of 8bits length (the first byte of a register). The field is configured "individual_accessible, so UVM should only access that FIELD. The reg2bus should generate that byte request to be written. In other words, the vector "addrs" should have only one byte address. Going to the code, i see that initially the addrs has the 4 address ( the whole register) and when it comes to the "if (rw.element_kind == UVM_FIELD) begin" and it will pop_back()/remove all the exceeding bytes that doesn't need to complete "n_bits_init" of the field access. The problem is here: UVM has //while (addrs.size() > (n_bits_init/(bus_width*8) + 1)) and i think it should be while (addrs.size() > ((n_bits_init-1)/(bus_width*8) + 1)) //ejonalv possible error in UVM? check That is because in case we want to write 8 bits, it will calculate 8/8+1=2 address in the UVM version, but in fact it should require only 1 address. This is of course applicable for the READ variation. Did i misunderstand something? It is very hard to go through the register model without proper documentation in the code. I am looking forward your answer Best Regards Jonathan
  2. Hi everybody.. Well i am new with systemC and working for the first time on it... I have tried to implement a basic D Flip Flop circuit. The aim is to connect two D-Flip Flop in series to form a Johnson counter. (But right now i am trying to test only 1 flip flop) The code is as follows: SC_MODULE(dff){ sc_in_clk clk; sc_in<bool>d; sc_out<bool> q; void dff::pro_dff() {q=d;} SC_CTOR(dff){ SC_METHOD(pro_dff); sensitive<<clk.pos();} }; SC_MODULE(my_mod){ sc_in_clk clk; sc_in<bool>a; sc_out<bool>b; dff *d1; void do_pro() { while (true) { d1->d(a); d1->q(; wait(); } } SC_CTOR(my_mod){ d1 = new dff("My_dff"); d1->clk(clk); SC_THREAD(do_pro); sensitive<<clk.pos(); } }; But when i run this program in sc_main it gives port binding error. what is wrong with the port binding?... and also please tell me that is the correct port binding method in systemC. I am using systemc v 2.1. The error message is as follows.. Error:<E109> complete binding failed: port not bound: port 'TEST_UNIT.My_dff.port_2' <sc_out> In file: ....\systemc-2.1.v1\src\sysc\communication\sc_port.cpp196 Please help me to resolve this problem.. thanks in Advance.
  3. Hi all! I have an error that I never had before with AMS. I have a few sc_modules with in and out TDF ports. Inside these sc_modules I have sca_modules, which are connected to those in and out TDF ports. This have been working fine until now, but I created a new class of module exactly the same way as the others and I have this error. I checked in the library and it seems like my sca_module is not assigned to any view: if (view_interface == NULL) { std::ostringstream str; str << "Error: " << name() << " a sca_module must be associated with a concrete view!" << std::endl; str << "It is not allowed to instantiate the sca_module base class." << std::endl; SC_REPORT_ERROR("SystemC-AMS",str.str().c_str()); } I know that maybe it not clear. I can give more details. But I am totally lost with this. Any ideas? Thanks
  4. g++ -g -I. -I.. -I /home/Desktop/systemc-2.3.0/include -c mesh_external_NI_main.cpp In file included from ./../include/systemc:72:0, from ./../include/systemc.h:244, from mesh_network/mesh_external_NI.h:5, from mesh_external_NI_main.cpp:5: ./../include/sysc/kernel/sc_module.h:32:39: fatal error: sysc/kernel/sc_kernel_ids.h: No such file or directory compilation terminated. make: *** [mesh_external_NI_main.o] Error 1
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