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Found 5 results

  1. I am going to simulate the following code but getting the error I am newbie to systemc (in fact C) your valuable input will help me to understand the error arith.h arith_proc.cpp cmd.h result_proc.cpp write_result.cpp Simple_Bus_csim.log
  2. I needed to step thru an enum in a testbench today. As it took me a while to figure out how to do it, I post a small example here. I want to do it without making any assumptions of the values of the enums (values are the default type of int, in this case). Reference: SystemVerilog doc "1800-2012.pdf" Section 6.19 Enumerations module top; //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek; //to show default assignments typedef enum {alpha, beta, gamma, delta, epsilon} greek; greek letters2; initial begin $display("****** Walk thru an enumeration example. ***********"); for (greek letters=letters.first(), int walk=0; walk < letters.num(); letters=letters.next(), walk++) begin $display(" %0d *** %0s", letters, letters.name); end end endmodule : top Output: ****** Walk thru an enumeration example. *********** 0 *** alpha 1 *** beta 2 *** gamma 3 *** delta 4 *** epsilon I'm also posting here, because when I am trying to remember how to do something, I find it often easier to find my postings online than an example in my own code. I thought I did this nicely with a foreach loop, but cannot find it, so may be imagining it. I was not keen on having to use variable walk. If someone can show me how to do this with a foreach loop or without using an extra variable, like I did with "walk", please do. Noted failures: for (greek letters=letters.first(); letters!=letters.last(); letters=letters.next()) begin //shows only 0-3 for (greek letters=letters.first(); letters<=(letters.num()-1); letters=letters.next()) begin //neverending loop
  3. Hi All, It seems that there is a problem for automatically updating components fields registered with uvm_field_* macros. It works fine if the field is of type int, but it fails if the field is of type enum. Do I miss something? (I tested this code with both UVM 1.1-d and UVM 1.2) class hs_driver extends uvm_driver #(hs_packet); hs_type_t driver_type; int my_param = 10; `uvm_component_utils_begin (hs_driver) `uvm_field_enum (hs_type_t, driver_type, UVM_ALL_ON) `uvm_field_int (my_param, UVM_ALL_ON) `uvm_component_utils_end [...] endclass: hs_driver class test_bench extends uvm_component; `uvm_component_utils (test_bench) hs_driver host; hs_driver device; [...] virtual function void build_phase(uvm_phase phase); super.build_phase(phase); uvm_config_db#(hs_type_t)::set (null, "*.device", "driver_type", DEVICE); uvm_config_db#(int)::set (null, "*.host", "my_param", 888); host = hs_driver::type_id::create ("host", this); device = hs_driver::type_id::create ("device", this); endfunction: build_phase endclass: test_bench Printing test topology: ------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------- uvm_test_top simple_test - @1863 mtb test_bench - @1939 device hs_driver - @2089 rsp_port uvm_analysis_port - @2162 recording_detail integral 32 'd1 seq_item_port uvm_seq_item_pull_port - @2130 recording_detail integral 32 'd1 driver_type hs_type_t 32 HOST -> should have been DEVICE! my_param integral 32 'ha recording_detail integral 32 'd1 host hs_driver - @2024 rsp_port uvm_analysis_port - @2095 recording_detail integral 32 'd1 seq_item_port uvm_seq_item_pull_port - @2058 recording_detail integral 32 'd1 driver_type hs_type_t 32 HOST my_param integral 32 'h378 -> In this case (for an integer) the field has been updated followin uvm_config_db recording_detail integral 32 'd1 recording_detail integral 32 'd1
  4. How do I display the name string of the UVM_VERBOSITY? I have been using this to report the verbosity level, but it returns an int. m_rh.get_verbosity_level() How would you display the enumerated name as opposed to the enumerated value? I'm looking at section "6.19 Enumerations" of the LRM (1800-2012.pdf) and close, but not there yet, so I punt this question out into the ether. .name() seems like it should be in there somewhere.
  5. When agents are configured, I typically see something like this: uvm_config_db#(int)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE); Isn't UVM_ACTIVE of type bit? I see it 'described' here in an enum and given a default value. src/base/uvm_object_globals.svh: typedef enum bit { UVM_PASSIVE=0, UVM_ACTIVE=1 } uvm_active_passive_enum; So shouldn't the uvm_config_db line not be: uvm_config_db#(int)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE); but instead be: uvm_config_db#(bit)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE); ? thx, (I sense that I probably don't have a solid enough understanding of enum and the relationship between bits and ints.)