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Showing results for tags 'end'.
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ljepson74 posted a topic in UVM SystemVerilog DiscussionsQ1) If I use a fork-join_none to spawn a process in a phase, and then that phase ends (b/c objection is dropped), is the process terminated or allowed to complete? I seem to be seeing that the process is terminated (but was expecting that it would be allowed to complete) and wanted to confirm that this is the expected behavior. Q2) Where is this behavior best documented? (Context: I was moving my timeout-timer from main_phase to pre_reset_phase, so that its time begins at time==0. If processes are killed when a phase ends, I suppose I should move it to run_phase to align it with time==0, ..... or start using the heartbeat component, which I have not gotten around to doing yet, but have been thinking a lot about.)
mrforever posted a topic in UVM (Pre-IEEE) Methodology and BCL ForumHi all, How to end simulation when there are forever-loops in sub-sequence and monitor? I have tried set_drain_time, but it doesn't work. If I remove the forever-loops in sub-sequence and monitor. The simulation ends when drop_objection executes done successfully in top-sequence after all the item being sent. By the way, I want to monitor signals of DUV during all the simulation time until the last item being sent. Could anybody tell me the trick? Thanks in advance.