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Found 1 result

  1. Hello, I'm writing a module in SystemC which basically works as follows: it receives a string of bytes through a port p_in and a control signal through the port h. The module must save the bytes within a matrix matrix just if the h signal is true. Within the SC_THREAD I'm using I implemented this: void MY_MODULE::my_method(){ if(!rst){ //put all the output ports to 0 } while(1){ //The module waits while the signal h is false while(!h) wait(); //The iterations to fill in the matrix begin //The iterations must work just if h = true for(i=0; i<100; i++){ for(j=0; j<100; j++){ matrix.nmmatrix[i*matrix.width+j] = p_in; wait(); while(!h) wait(); } } } } The problem I have is that the counters i and j start to increment one clock cycle after h passes from false to true. The behavior I'm trying to simulate is that the counters i and j start to increment in the same clock cycle when h passes from false to true and the counters must not increment while h is false. Could you please give a hint of what I am doing wrong?
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