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ljepson74 posted a topic in UVM SystemVerilog DiscussionsI recently encountered SVA code which results in different results on different simulators. I've shrunk it to a simple example here. I believe this code should cause an error, but it does not on all tools. Can someone comment on how the 2017 LRM should be interpreted (and perhaps on the code). (I sense someone will comment on the driving signals in the code.) module top; bit clk; logic sig1; logic disable_assert; always begin #5 clk=0; #5 clk=1; end initial begin disable_assert=1'b1; sig1 =1'b0; $display("Hello World"); $monitor($time," **** sig1:%0b disable_assert:%0b",sig1, disable_assert); repeat (3) @(posedge clk); @(posedge clk); sig1=0; disable_assert=1; @(posedge clk); sig1=1; disable_assert=1; //2a. assertion would fail, but it is disabled @(posedge clk); sig1=0; disable_assert=0; //2b. now assertion is enabled and should fail** @(posedge clk); sig1=0; disable_assert=1; #20; $finish(); end property as_disable_testing; @(posedge clk) disable iff (disable_assert) !sig1; endproperty assert property (as_disable_testing); endmodule : top Question: Should there be a timing error at comment 2b, or not? Code is here to play around with: https://www.edaplayground.com/x/njR Picture: https://docs.google.com/drawings/d/1qQB4dB5w8_1jx73xta46RbmLzkparaNcxHNdLgi8YNY/edit?usp=sharing These are my thoughts: // It seems this small code snippet should cause an error, but tool results differ. // // // NOTE: Yes, I realize that I am using tools from BEFORE 2017, but comparing results to the 2017 LRM. // What is the correct LRM interpretation? What comments do gurus have about this code? // // //1) Run the code with Aldec Riviera Pro 2015.06, Synopsys VCS 2014.10, and with Cadence Incisive 15.20. // RIVIERA PRO and IRUN show assertion failures. // VCS does not show assertion failure. // //2a) This is time when sig1=1 assertion 'would' fail, but it is disabled (disable_assert==1) //2b) **On next clock cycle the assertion set to be enabled (i.e. disable_assert==0). // The SystemVerilog 2017 LRM (1800.1-2017.pdf) describes the behaviour. // At the start of the 2b time slot (see page 64 of SystemVerilog LRM 1800.1-2017), // PREPONED REGION: the values of the assertion are sampled (sig1==1) // ACTIVE/INACTIVE/NBA regions: the values are updated (sig1,disable_assert) // (so you can use either blocking "=" // or you can use non-blocking "<=" // and you will get the same result) // So for this time slot: sig1==0, disable_assert=0 // OBSERVED REGION: this is where the assertion is evaluated, using values sampled from // the preponed region (so sig1==1). // However, the value of disable_assert is not from the // preponed region, but simply whatever the value is, // as assigned in the active/inactive/nba region. // // // Section 16.6 of the SystemVerilog LRM (1800.1-2017 states: "The expressions in a disable condition are evaluated using the current values of variables (not sampled) ..." I believe this means from whatever is set in the Active/NBA region of current time slot. // // Section 16.12 of the same document states: "If the disable condition is true at anytime between the start of the attempt in the Observed region, inclusive, and the end of the evaluation attempt, inclusive, then the overall //evaluation of the property results in disabled." // // My conclusion: The sig1 value from 2a will be used in 2b when disable_assert=0; ***Assertion should fail.*** // // Picture: https://docs.google.com/drawings/d/1qQB4dB5w8_1jx73xta46RbmLzkparaNcxHNdLgi8YNY/edit?usp=sharing
Consider the following code and the assertion to check for unknown data. If the code will change so that there will now be an array of valids and datas, what is the best way to change the assertion, so that for each valid, the corresponding data is checked.? Can I do it one line? (I had been considering using a generate statement around it.) module top; bit clk; logic write_valid; logic write_data; always clk = #5 !clk; initial begin clk=0; write_valid=0; #7; write_valid=1; #100; $finish; end as_showme : assert property (@(posedge clk) disable iff (!write_valid) (!$isunknown(write_data)) ) else begin $display("*** ERROR. write_data was unknown. ***"); end endmodule
Hi all, Please, I would like to know if someone here is aware of any update/progress related to the "Implementation of a SystemC Assertion Library" developed by Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten and Jacob Smit. Is that library available for download ? Thanks in advance, Fabio
ljepson74 posted a topic in UVM SystemVerilog DiscussionsAssertion experts, I know how to do a check of new_data_io (see below) in terms of 'regular' SV code, but will someone comment on how/if I can put this into a nice assertion to put into my interface? All based on posedge clk: valid_io - indicates valid data data_io - the data new_data_io - signifies that data_io has changed since the previous valid_io cycle So, when (valid_io && (!new_data_io)), the receiver can just use the most recently valid data. (The fact that there can be cycles of !valid_io, while this assertion is active, is what's throwing me off. Well, and also the concept of retaining previous state of data_io. Perhaps this might not be suitable for an assertion and I should just stick with a small process to do the check.) thx for any feedback, Assertion Novice (Why ever did I loan out my book Art of Verification with SystemVerilog Assertions by Faisal Haque?)