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Found 5 results

  1. I need to create a TLM module (that here we will call top_level) containing an array of TLM target modules (defined by class reg). As a consequence, the top_level module should implement the tlm_bw interface, and contain an array of initiator sockets, each bound to a target socket of the reg modules. Is it possible to implement this hierarchy by using the sc_vector construct? Here is a snapshot of the code that I am trying to implement, to give a clearer idea: Top level #include "reg.h" class top_level : public sc_module , public virtual tlm::tlm_bw_transport_if<> { private: sc_time time; sc_vector<reg*> register_file; tlm::tlm_generic_payload reg_trans; public: sc_vector <tlm::tlm_initiator_socket<>*> initiator_socket; ... }; Target module: class reg : public sc_module , public virtual tlm::tlm_fw_transport_if<> { public: tlm::tlm_target_socket<> target_socket; virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& t); reg(sc_module_name name_); ... }; When trying to compile, the compiler returns this error: error: ISO C++ forbids declaration of ‘sc_vector’ with no type error: expected ‘;’ before ‘<’ token referring to both the instances of sc_vector, as if neither my class nor the initiator_socket class were recognized as datatypes... Best regards, S.
  2. Hello, I've been trying to instantiate (if I'm not mistaken) an array of submodules that were created using sc_vector. So far, I've followed the recommendations for using custom creator functions, but I'm kind of lost at how to actually make it work. Especially with sc_bind, which keeps returning me errors. The module master houses an array of ports that will be connected to a corresponding number of slaves. Order of connection does not matter. I'm using MSVC++ 10. The code is as follows: class top : public sc_module { //Submodule declarations master master_i; sc_vector<slave> slave_i; public: // Constructor top( sc_module_name module_name , int k ) : sc_module( module_name ) , master_i("master"), slave_i("slave") { slave_i.init(N_SLAVE, sc_bind(&top::create_slave, this, sc_unnamed::_1, sc_unnamed::_2)("slave",k)); sc_assemble_vector(slave_i, &slave::target_port).bind(master_i.initiator_port); } The creator function, which is a member of the class top, is as follows: static slave* top::create_slave(const char* name, size_t idx) { slave* s = new slave(name,1); // Hardcoding not intended; it's just to get it to // compile return s; } slave class constructor prototype: slave( sc_module_name module_name , int k ); Errors that I have so far: 1>c:\systemc\systemc-2.3.1\src\sysc\packages\boost\bind.hpp(63): error C2825: 'F': must be a class or namespace when followed by '::' 1> c:\systemc\systemc-2.3.1\src\sysc\packages\boost\bind\bind_template.hpp(15) : see reference to class template instantiation 'sc_boost::_bi::result_traits<R,F>' being compiled 1> with 1> [ 1> R=sc_boost::_bi::unspecified, 1> F=slave *(__cdecl *)(const char *,size_t) 1> ] 1> c:\users\khairul\dropbox\cours\systemc\examples\source\11\master_slave\top.h(32) : see reference to class template instantiation 'sc_boost::_bi::bind_t<R,F,L>' being compiled 1> with 1> [ 1> R=sc_boost::_bi::unspecified, 1> F=slave *(__cdecl *)(const char *,size_t), 1> L=sc_boost::_bi::list3<sc_boost::_bi::value<top *>,sc_boost::arg<1>,sc_boost::arg<2>> 1> ] Any ideas? Thanks,
  3. Hi, So I have a submodule having an array of boolean input ports. Now in the top module, I define an sc_vector of the submodule type. Also, I define an array of sc_vector signals to be bound to. Questions: Can I use an array of sc_vectors? Any conventions on using them? eg: can I write sc_vector < sc_signal <bool> > operand_vec[max_operands]; If no, then is there any work around for this? Also, I now need to assemble and bind these ports: The code below doesn't seem to work. Both the stack_cnt_vec and operand_vec are initialized properly. for(int i=0;i<max_operands;i++){ operand_vec[i].init(10); } for(int i=0; i<10; i++) { sc_assemble_vector( stack_cnt_vec, &StackController::operands[i]).bind( operand_vec[i] ); } Thanks a lot for your time.
  4. Do fixed-size arrays not support .size()? Or, am I doing smthg wrong below? Running irun 13.1, I am told that .size() "is not a valid built in method name for this object". If they do not, is this b/c a. the expectation is that someone used a parameter/constant to specify the size of the array and that they can just use it everywhere else they might need it b. fixed sizes arrays were part of pre-SystemVerilog Verilog and as such missed this convenient feature. ? Just before publishing, I discovered section "20.7 Array querying functions" in the 1800-2012.pdf, SystemVerilog spec: $size() module top; int farray[10]; //fixed array initial begin //1 for (int jjj=0; jjj<10; jjj++) begin //works /*2*/ for (int jjj=0; jjj<farray.size(); jjj++) begin //doesn't work //3 for (int jjj=0; jjj<$size(farray); jjj++) begin //works farray[jjj] = $urandom_range(121,0); end $display("******************************"); for (int jjj=0; jjj<10; jjj++) begin $display("%0d: %0d",jjj,farray[jjj]); end end endmodule : top
  5. In SystemVerilog we can have dynamic unpacked arrays and they can be passed to a function/task. I was wondering if there is a way to pass dynamic packed arrays to a function/task. For example consider the following code: module test; logic [3:0] A; logic [7:0] B; task automatic double(ref [3:0] val); val = val * 2; $display("%b",val); endtask initial begin A = 3; double(A); B = 5; //double(; ** Error because of size mismatch end endmodule here the task can only have a 4-bit input argument so if B is passed an error occurs. I am interested to know if there is any way to pass packed arrays of different size to a task/function. In previous example if the arrays were unpacked I could use: task automatic double(ref val []); but I have no idea what I should use for packed arrays. In VHDL having variable size input arguments is very easy. For example the same code can be written like this: use std.textio.all; entity test is end entity; architecture arch of test is procedure double(val: bit_vector) is variable temp : bit_vector(val'left downto val'right); variable l : line; begin temp := val sll 1; write(l,temp); writeline(output,l); end procedure; begin process variable A : bit_vector(3 downto 0); variable B : bit_vector(7 downto 0); begin A := "0011"; double(A); B := "00001111"; double(; wait; end process; end architecture; I appreciate any idea on this. Thanks