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ljepson74 posted a topic in UVM SystemVerilog DiscussionsQ1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking. case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share case2) XYZ testbench. the same case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VHDL. Or, we can bind the sv interface to the ABC-XYZ connection, to reuse the protocol checking of that interface. Without using a macro or `include of the protocol checking code, I'd like to just have a package or some place where we store the protocol checking code and can reuse it, whether in an sv interface, or a module which we bind to the VHDL. Looking into this, and researching putting assertions into packages, I discovered checkers. Hence this line of questioning. Please share your thoughts and experience.
I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification. I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim. What is the best way to use the SystemC open source simulation to make calls to a VHDL simulator like modelsim while reducing the license usage of modelsim? Can you share your experience and lessons learned regarding mixed language sims? Thanks Paul