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Showing results for tags 'UVM_PHASE'.
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ljepson74 posted a topic in UVM (Pre-IEEE) Methodology and BCL ForumT or F: Objections should not be used in the uvm phases which are functions (i.e. build_phase, connect_phase, check_phase, ...). If True, why?
ljepson74 posted a topic in UVM SystemVerilog DiscussionsQ1) If I use a fork-join_none to spawn a process in a phase, and then that phase ends (b/c objection is dropped), is the process terminated or allowed to complete? I seem to be seeing that the process is terminated (but was expecting that it would be allowed to complete) and wanted to confirm that this is the expected behavior. Q2) Where is this behavior best documented? (Context: I was moving my timeout-timer from main_phase to pre_reset_phase, so that its time begins at time==0. If processes are killed when a phase ends, I suppose I should move it to run_phase to align it with time==0, ..... or start using the heartbeat component, which I have not gotten around to doing yet, but have been thinking a lot about.)
Hi UVM Experts, I am facing some issue with UVM phase. I have registered one sequence to pre_configure phase of one sequencer which is doing some chip configuration. In my base test pre_configure phaseI am waiting for that configuration to get over usng hierarchy of RTL path signal. RTL takes some time after configuration gets over to toggle the indication of chip ready which i am waiting in base test pre_configure phase. I observe that sequence gets over but immediately test also gets finished even i raised the objection from base test pre_configure phase. Would you please point me if it is exptected? I think till all raised objections are not lower simulation will not be over. and I want my test to wait once sequence is over and RTL toggles ready signal. Thanks in advance for your time. Thanks, Akshay