Jump to content

Search the Community

Showing results for tags 'UVM 1.2'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus Pre-Release Discussion
    • Portable Stimulus 1.0
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 2 results

  1. I have two sequences seq_a and seq_b that can be run on sequencer. In my component i have the code to set the default sequence. Below is the code in component and i am trying to set the default sequence as "seq_b" task run_phase(uvm_phase phase); uvm_config_db #(uvm_object_wrapper)::set(null, "uvm_test_top.my_sequencer.main_phase", "default_sequence", seq_b::type_id::get()); sequencer.start_phase_sequence(phase); endtask: run_phase With this code in component, if i pass the following command lines argument to change the sequence to seq_a: "+uvm_set_default_sequence=*,main_phase,seq_a" The sequence that runs on sequencer is still seq_b only, it was not modified to seq_a. Sequence control from command line works when i comment the default_sequence code in run_phase. It looks for me that "+uvm_set_default_sequence" can't be used when i am setting the default_sequence inside the run_phase. It will be good if "+uvm_set_default_sequence" overrides the default_sequence that was set in run_phase. So that it gives more flexibility from command line. Please give your comments on this behavior on UVM 1.2.
  2. The first video series Introducing What's New in UVM 1.2 is out. Also, here is the UVM 1.2 Class Reference This video series covers the changes and new features introduced in UVM 1.2. It is intended for engineers who are already somewhat familiar with UVM. The series comes with CODE EXAMPLES THAT WORK. That's right, real working code and not just a snippet on a slide. The series has the following parts, covering different areas of UVM 1.2 changes. Recommend viewing in 720p quality or higher. uvm_object must have constructor code example Config DB uvm_enum_wrapper code example set_config code example Objections objections code example set_automatic_phase_objection code example Sequences sequence code example uvm_integral_t type uvm_integral_t code example Reporting (major changes) reporting code example Phasing phasing code example Factory extending factory code example parametrized uvm_event uvm_event code example Transaction recording (coming soon) I hope you find it useful. Let me know what other topics you'd like to see. Note: The videos are based on UVM 1.2 release candidate. I do not expect the features covered in the series to change for the final release. The above code examples will always work. If needed, they will be updated for the final UVM 1.2 release.
×