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  1. To view this announcement on the IEEE web site click here. Purpose Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. Need for the Project As the electronics industry builds more complex systems involving large numbers of components, the challenge of verifying such systems multiplies by orders of magnitude. In order to bring costs and time to market down, standardization must happen to enable as much modularity and reuse across verification components as possible. The UVM standard will propagate an API that will manage this explosion in verification complexity, allowing the entire industry to write and reuse verification components both (a) internally in companies having geographically widespread teams, and (externally between vendors and user companies in the electronics industry, who are developing, selling and using verification components Call for Contribution Please review the IEEE P1800.2 ™ PAR and, if you are interested in participating, Register for the first working group meeting scheduled to occur on August 6th, 2015 from 12pm – 2pm Eastern Daylight Time (EDT) / 9am – 11am Pacific Daylight Time (PDT). Please feel free to connect with the Working Group Chair, Thomas Alsop at thomas.r.alsop@intel.com or IEEE-SA staff Jonathan Goldberg at goldberg.j@ieee.org directly for further information.