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I am trying to incorporate FC4SC into our SystemC structure, we have multiple modules and we want to capture SFS with FC4SC, we have a BaseCoverModel and I wanted to know if i want to disabled some Coverpoints in a sub class, can someone tell me how we can do that ?

I would like to know what is the recommended place to implement functional coverage 1) non temporal functional coverage - coverpoints I understand these can be implemented in monitors, scoreboards, subscribers, coverage collectors (though I don't know what the last 2 really are) 2) temporal functional coverage - cover directives I understand these can be implemented in interfaces, modules or programs

I need to implement coverage across multiple interfaces. For example in the arbitor designs, it is of interest to see if multiple requests from different agents are driven at the same time. All the texts have only discussed coverage specific to the interface or transaction. I have an idea of implementing this, but not sure if it is the right way forward. Here is my idea: First place, instead of extending the coverage class from uvm_subscriber, I intend to extend it from uvm_scoreboard. This is because, uvm_subscriber is tied to a transaction type, whereas uvm_scoreboard is not. The code below might not be syntactically right, and I intentionally leave the factory registration, new(), build() etc. in order to be concise. `uvm_analysis_imp_decl(_transaction_A) `uvm_analysis_imp_decl(_transaction_B ) `uvm_analysis_imp_decl(_transaction_C ) class coverage_class extends uvm_scoreboard; bit req_a; //request coming from transaction A bit req_b; //request coming from transaction B bit req_c; //request coming from transaction C uvm_analysis_imp_transaction_A #(trans_a, coverage_class) trans_a_port; uvm_analysis_imp_transaction_B #(trans_b, coverage_class) trans_b_port; uvm_analysis_imp_transaction_C #(trans_c, coverage_class) trans_c_port; covergroup cg; coverpoint req_a; coverpoint req_b; coverpoint req_c; cross req_a, req_b, req_c; //Want to capture a case where all 3 requests go high at the same time from 3 different interfaces. endgroup //write function to capture trans_a virtual function void write_transaction_A(trans_a t); req_a = t.req; cg.sample(); endfunction //write function to capture trans_b virtual function void write_transaction_B(trans_b t); req_b = t.req; cg.sample(); endfunction //write function to capture trans_c virtual function void write_transaction_C(trans_c t); req_c = t.req; cg.sample(); endfunction endclass I also realize that, when 2 requests are high at the same time, there might be a delta delay between the two. Say "write_transaction_A" happens a delta before "write_transaction_B" (still the same timestamp). So when transaction_A happens, req_a is set to 1 and the covergroup is sampled. At this delta time, transaction_B has not occurred so, req_b is still 0. In the next delta cycle, write_transaction_B happens and so, req_A as well as req_B is asserted, and covergroup is sampled again. I see 2 issues here: 1. We are sampling the covergroup more than actually required. Is there a better way of sampling the covergroup? 2. Where do we clear the req_A/req_B/req_C variables in order to be sampled again. Is there a better way of accomplishing the same task? Please share your thoughts.

For AXI write transaction axi wready signal determines whether the slave can accept the data. For write burst performance i need to capture the latency between "WREADY" and "next WREADY" signal. For example this ready signal is getting low at clockno 8 and it should remain low for clockno 9 and 10 and the clockno 11 the signal will be high as per the slave configuration. when the multiple burst transacion occurs with (write length > 2) the ready signal behavior will be like above. I want to write a functional coverage like "wready" and next "wready" signal latency is 2 which means when the ready signal is low it will low for 2 clk cycles and then ready will high(if there are multiple write burst transaction).

Hi all, After developing a virtual platform using SystemC with TLM, and also several peripherals (IP) model in high-level (LT), I realised that if in RTL design there is a UVM to say that the design is "okay". How about in high-level? Is there any methodology that we could adopt? If there is none, may I ask for your suggestion on how to verify our own SystemC TLM (LT) design? The SystemC Verification subforum seems to be obsolete, so I posted it here. Really appreciate any kind of advice and solution. Thank you. Regards, Arya.

While I am waiting for an answer from the simulator vendor, I think I can form a non-tool-specific question about my problem. I am running a simulation which dies when I collect functional coverage. I can turn on/off functional coverage collection and when it is on, at the very end of simulation, I get: "ncsim: *F,INTERR: INTERNAL EXCEPTION". It seems to be that while coverage is gathered, the problem occurs. I can run tests which flow thru some channels of the dut and don't have the problem, but thru a specific channel of the dut, I often encounter the problem. question1: What is classified as functional coverage? I'd like to leave functional coverage collection on and comment out all coverpoints/covergroups. (Actually I think I have, or am close, and the error still occurs.) So, I am wondering, what must I grep for to remove to be sure that functional coverage collection has no meaning? My thought is to divide and conquer. Am I not just looking for "coverpoint" and "covergroup", but also "assert" (as some code might have assertion based functional coverage)? Is there anything else? question2: (This is perhaps a bit tool specific.) If the -covdut, or scope of where coverage should be gathered is targetted to a sub-sub-module, would you expect that (possibly bad) coverage code at a higher level (or different area) would have zero affect on the coverage collection? (I've unsuccessfully tried to leave functional coverage collection on, but to move the target-scope to a trival part of the design, to see if the problem goes away.)

Hello, I am creating a functional coverage model. I am binding my coverage model with the design using the "bind" statement. I need to access some internal signals of a design instance inside a design module for using in my functional coverage model. However I get an error when I try that. Below is what I am trying => In the RTL design module "dut_berc", there is a instance "dut_berc_cmd". I need to access the signal "pct_err_status_vec" in this "dut_berc_cmd" module. So in design => ----------------------------- module dut_berc #(....) (clk, reset, .... ); dut_berc_cmd #(...) u_dut_berc_cmd (..); ----------------------------- ----------------------------- module dut_berc_cmd #(....) (..... ); logic [PCT_DEPTH-1:0] pct_err_status_vec; <----- This is the signal I need to sample inside my functional coverage model ----------------------------- In the top level TB file, the bind happens => --------------------------- bind dut_berc dut_cov_berc #() FUNC_COVERAGE (.*); --------------------------- In "dut_cov_berc" => ------------------------- module dut_cov_berc #(...) ( input [PCT_DEPTH-1:0] u_dut_berc_cmd.pct_err_status_vec, ........ ) ------------------------- However I get the following error when I try this => ----------------------------------- ** Error: /view/....../src/dut_cov_berc.sv(36): near ".": syntax error, unexpected '.', expecting ')' ----------------------------------- I tried directly accessing the signal in my functional coverage module but it gave an error that it is unable to find this signal. Please let me known what is the correct way to access design signals present in a hierarcy in the functional coverage model? Thanks.