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Showing results for tags 'vivado'.
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Hello everyone, i am very new to both systemc and HLS. I have systemc code that I am trying to synthesize using Vivado HLS 2019.2 (since it still supports Systemc). The systemc code works fine but was not originally written for Synthesis and I am trying to make it synthesizable. I have a problem since the source code has arrays of ports for example: sc_in<sc_int<8>> input [10]; sc_out<sc_int<8>> output[10]; that are connected to arrays of signals, example: sc_signal<sc_int<8>> sig[10]; What is the best way to making the code synthesizable? I tried pragmas but the arrays are defined in the SC_Module in the header files and not inside functions, I believe this is causing the following error: ERROR: [HLS 200-70] '#pragma HLS ARRAY_PARTITION variable=input type=complete dim=0' is not a valid pragma I also tested using sc_in<sc_lv<80>> input , however I am not sure of connecting the port to a signal array since using input.read().range(0,8)(sig[0]); is causing errors and also i am not sure how to connect sc_out with another sc_out when using sc_lv. Thanks in advance for your help!! -
To All Design and DV Engineers! Xilinx Vivado 2020.1 Supports UVM 1.2 and many features of Systemverliog. It supports the same in WebPack (Freeware) Version. There are some limitations on side of assertion cover properties but rest it compile complete SV and UVM including constraints and randomization. Learning UVM without hands-on is difficult. I believe this is opportunity for students, engineers and hobbyists to skill up without relying on paid or online tools as now you can run UVM on your system. For getting started, even though there are many UVM generators, I believe the starters need simple easy to use UVM generator tool. I found the ones available online like Easier UVM or UVMF quite difficult to use and even interact with. I developed a open-source tool "tbengy" to generate a UVM TB and Makefile that will readily get you started and will run on Vivado Simulator. You can read the instructions on https://github.com/prasadp4009/tbengy Hope it helps you all! -
Hi everyone, As part of my job I try to implement a FFT function in my ZedBoard. I found some example including one in the SystemC folder unfortunately not synthesizable. Furthermore, I use a free version of Vivado HLS and this tool is very restrictive (few things are synthesizable). So, I will going to have to code my own version of this function (8k/16k/32k FFT). For doing this, I started by cut the FFT's mathematical formula and try to code a exponential function. I realized I can't use the "math.h" library and then I have to code all with only logic gates. At this level, I prefer to code directly in VHDL. Does anyone have a experience with this synthesis tool and can give me a simpler way to achieve my goal ? Maybe I see the problem of the wrong angle. Best regards
