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Found 73 results

  1. In case of UVM ,config_db can be accessed in any component or object which helps mainly the dynamic creation of component/models.Whether any option is present in SYSTEM C ?
  2. Hi, I have a doubt about requirement of raise/drop_objection. Why does a compiler need objections in run_phase? Why can it not just wait for time given like 100ns as following example? Ex. task run_phase(uvm_phase phase); //phase.raise_objection(this); #100ns; //phase.drop_objection(this); endtask
  3. Hi all, I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue. In the data_phase (the data channel driving) from the MASTER driver, I need to drive the RREADY signal. There are 3 handshake types described in the protocol specifications: valid before ready, ready before valid and ready and valid at the same time. In case of valid before ready, I want to wait a certain number of clock cycles ( delay ) from the time that RVALID asserted and then to assert the RREADY signal. From my understanding, all the delay information should come from the transaction(sequence_item). The problem is that I generate a new transaction (sequence_item) with get_next_item only when I drive the address channel (in address_phase); The data_phase works in parallel with the addr_phase and its independent of the address phase. Also the data_phase needs multiple delay values (one for each data received from DUT, ex. arlen+1) while I only generate one transaction that contains the address channel informations. Code example: task run_phase(uvm_phase phase) fork forever begin ... seq_item_port.get_next_item(req); address_phase(req); seq_item_port.item_done(); end forever begin data_phase(); end endtask : run_phase task address_phase(axi_item item); // Drive the address channel ... endtask : address_phase task data_phase(); // Wait for the rvalid signal while(!vif.rvalid) @(posedge vif.clk); // Insert delay between rvalid assertion and rready assertion repeat(<problem!!!!>) @(posedge vif.clk); rready = 1; ... endtask : data_phase I don't know what variable (sequence_item variable) to set in the <problem!!!> Can anyone give me an advice regarding this problem. I repeat, I want all timing related data to be set from the sequence_item Regards, Adrian
  4. Hello there, As per Mentor's UVM guidelines 5.2 [1], reset_phase() will be obsolete in future releases. During DVCon 2014, Cadence recommends to use run_phases() on slide 5 of [2]. With the release of UVM-1.2, I believed that the sub-phases of run_phase are now stable and clean. Now with the recommendations above, it seems that the it's better to stick with run_phase() itself. As UVM delelopers, what are your views about it ? What do you recommend ? My intention is not to start a flame war of any kind. But to understand which route to opt in order that most of my UVM code would be compatible with UVM 1.3. All in all, it appears that there is a miscommunication on the web. [1]: https://verificationacademy.com/cookbook/UVM/Guidelines [2]: http://proceedings.dvcon-europe.org/2014/presentations_and_papers/T5_3_presentation.pdf regards, Chitlesh
  5. Hi All, I have a sequence sending a created and randomized item using `uvm_send. The driver receives an item using try_next_item. Upon receiving, it drives the item and calls item_done. Using debug message after item_done, I can clearly see that item_done is called and returned but `uvm_send in sequence is still blocked and not doing forward to send next item (it implements a loop). Can anyone help me with possible reasons why `uvm_send would not return even when driver has called item_done and come out of item_done. Thanks in advance! Ninad
  6. Hi all, I'm doing verification for an PHY between SPI master and a memory chip. I make two agents one for master to transfer the request, one mimics the memory slave to reply. PHY will be hooked up to two interfaces that of SPI Master and Memory. During sending request and reply data, Chip Select Pin (in SPI interface) must go low to enable the transaction. But I don't know how to control this pin when It sends the reply from memory. Because this pin is not an interface of memory slave agent. Could anyone give me some advice? Could I use phases to control the env that has different agents? Thank you, Nhat
  7. Hello, I'm trying to implement an AXI Slave VIP and have few questions regarding the implementation. In this case, the DUT is the master. The AXI Slave checks the interface for valid read /write signals and performs a read/write operation from a memory model. It returns back the write response/read data back to the DUT. 1. Since this is a slave VIP , do I need a slave sequence which runs forever sending transactions to the driver ? This is similar to the UVM example where the monitor and sequencer are connected by an analysis port and the sequence calls the peek function to check if a valid transaction is available from the monitor. (OR) 2. Can I skip the sequence/sequencer part and just connect my monitor and driver using an analysis port and pass on the observed transaction from the monitor to the driver for further action ? (OR) 3. Im thinking of a 3rd alternative of just using the monitor to the observe the interface and drive back the write response/ read data back using the monitor itself and leave the driver empty. Please let me know your valuable thoughts and suggestions. Thanks, Madhu
  8. Hi, As per my understanding, connect_phase does not start until all build_phase do not complete. How is this mechanism controlled? I did not find anything in uvm reference manual about this. Please let me know if there is any. Thanks.
  9. Hi all I'm trying to build a generlc verification environment for specific modules of mine, that essentially only differ (besides their actual implementation) by the number of inputs/outputs of a certain interface standard and the data_size of each of these interfaces. This leads to the point, that I like to have an environment, where I can set the number of interfaces and for each of these interfaces the data_size. Unfortunately this simple setup of non-dynamic pre-compile settings is getting me in a lot of trouble. (1) Sequence_Item class input_item #(int unsigned data_size) extends uvm_sequence_item; `uvm_object_param_utils(input_item) rand logic[data_size-1:0] data; ....... The first question that comes to mind writing this code is the following: Is it possible to factory overwrite a param. class with another specilisation of that same class (e.g. define a driver with input_item<32> and then factory overwrite it with input_item<42>)? Otherwise a item_base class would be necessary that than would be extended by this class. (2) Analysis Ports class env extends uvm_env; .... // need N = number of interfaces analysis ports between each monitor and scoreboard uvm_analysis_port #(input_item#(17)) ap_1; uvm_analysis_port #(input_item#(12)) ap_2; ..... uvm_analysis_port #(input_item#(42)) ap_N; .... Due to the different input_items all ports are of a different type. Therefore it is not possible to create an array of N=number_of_interfaces, which leads to this not being possible to implement. Furthermore the analysis_port/export classes cannot be overwritten through the means of the factory. (3) Virtual Sequence class top_vseq_base extends uvm_sequence #(uvm_sequence_item); `uvm_object_utils(top_vseq_base) uvm_sequencer #(input_item#(17)) seq_1; uvm_sequencer #(input_item#(12)) seq_2; ... uvm_sequencer #(input_item#(42)) seq_N; In the virtual sequence I essentially run into two problems: 1. The first one is the same problem as in (2) of not being able to create an array of different types or having a pre-processor for-loop 2. The other one is the fact, that I'm not able to get access to the number N . Even if they were all of the same type and I would declare a dynamic array, there is no build_phase and no way to get informations through either the config_db or "p_sequencer.variable". I could put a member variable into the virtual sequencer, but I'm not sure if it is a good idea/possible to create a dynamic array in the body method. General Solutions so far: I only see two solutions here ... 1. Defining a gigantic input_item with data_size of 256/512 and then cut it everywhere. But unfortunately I will be in need of an array of completely different items in the next version of this environment anyhow. The reason for that is, that I would like to group a bunch of M different interfaces into one environment, all of them running a different item. Therefore the analysis_ports would all run a different item. 2. Just building a code generator, in which the user sets all parameters, creating the necessary environment for the given DUT. If you have any input, I would be glad to hear it. Thanks Marcel
  10. To view this announcement on the IEEE web site click here. Purpose Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. Need for the Project As the electronics industry builds more complex systems involving large numbers of components, the challenge of verifying such systems multiplies by orders of magnitude. In order to bring costs and time to market down, standardization must happen to enable as much modularity and reuse across verification components as possible. The UVM standard will propagate an API that will manage this explosion in verification complexity, allowing the entire industry to write and reuse verification components both (a) internally in companies having geographically widespread teams, and (externally between vendors and user companies in the electronics industry, who are developing, selling and using verification components Call for Contribution Please review the IEEE P1800.2 ™ PAR and, if you are interested in participating, Register for the first working group meeting scheduled to occur on August 6th, 2015 from 12pm – 2pm Eastern Daylight Time (EDT) / 9am – 11am Pacific Daylight Time (PDT). Please feel free to connect with the Working Group Chair, Thomas Alsop at thomas.r.alsop@intel.com or IEEE-SA staff Jonathan Goldberg at goldberg.j@ieee.org directly for further information.
  11. Hi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object from configuration space. In env build_phase, I do set the configuration as below: uvm_resource_db#(io_config)::set("io_agent_0*","io_agent_config",m_io_config,this); And in io_agent, below code is used to get the configuration: assert(uvm_resource_db#(io_config)::read_by_name(get_full_name(),"io_agent_config",cfg,this) else uvm_report_fatal("io_agent","not able to get the configuration object"); Kindly let me know if there is anything wrong in the above usage. And also, can I do setting configuration through uvm_resource_db and getting it through uvm_config_db. Thanks A.Sunitha
  12. a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the details here) Creating the virtual interface container wrapper parameterized to the strongly typed interface helps here. but in the uvm component, a pointer needs to be created for the parameterised interface. If not wanting the classes to be parameterized, how the virtual interface handle can be created without specifying the parameter as either a default parameter in base class or override is necessary for creating handle?. The component will get the wrapper object from config_db and assign it (the virtual interface in the object) to the virtual interface pointer Thanks.
  13. Hi all, First I apologize if I am using the wrong forum for the question. Please, I would like to know whether someone here could give updates on uvm-sc status. When will a first public release be available ? Regards
  14. Hi All, I am facing an issue: One of the register field is configured as : field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1); field_a.set_compare(UVM_NO_CHECK); While doing a reset test, first I reset model then start test. But test fails with : UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00) Basically the fields declared as RO and UVM_NO_CHECK goes X ? Any idea what I am missing or doing wrong ? Thanks.
  15. I am trying to run a couple of test cases using script.But I am getting an error message after running the first test case.This stops the simulation.I am attaching the LOG with this mail.I don't understand why this is happening. I checked previous posts and added +UVM_OBJECTION_TRACE in the vsim command.But I am not able to find out the cause of the error.Can anybody help me?? # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1 total=1 # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_test_top): count=0 total=1 # AT TIME=0,APB MASTER IN RESET MODE # AT TIME=1200000,APB MASTER IN ACTIVE MODE # AT TIME=45400000,*************************** EXPECTED_DATA=1792474624,RECEIVED DATA=1792474624 # AT TIME=186600000,*************************** EXPECTED_DATA=222,RECEIVED DATA=222 # AT TIME=231800000,*************************** EXPECTED_DATA=1504340502,RECEIVED DATA=1504340502 # AT TIME=349000000,*************************** EXPECTED_DATA=2367782205,RECEIVED DATA=2367782205 # UVM_INFO Test_Cases/my_test.sv(40) @ 349000000: uvm_test_top [root objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 0 1 uvm_top # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO Test_Cases/my_test.sv(43) @ 349000000: uvm_test_top [my_component objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top all_dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 349000000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # # --- UVM Report Summary --- # # ** Report counts by severity # UVM_INFO : 12 # UVM_WARNING : 0 # UVM_ERROR : 0 # UVM_FATAL : 0 # ** Report counts by id # [OBJTN_TRC] 6 # [Questa UVM] 2 # [RNTST] 1 # [TEST_DONE] 1 # [my_component objections] 1 # [root objections] 1 # ** Note: $finish : C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430) # Time: 349 us Iteration: 68 Instance: /my_top # 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # Simulation Breakpoint: 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # MACRO ./run_do PAUSED at line 18
  16. Hi, I am diagnosed with ‘Wrist tendinitis’/’tenosynovitis’ due to RSI (Repetitive Strain Injury). Hence I started using speech recognition as much as possible. On windows, controls are 80% accurate and dictation is 50% accurate. With practice, I am trying to use keyboard and voice recognition just the same way a pianist would sing. I think with the wealth of research in speech recognition, it is possible to get a decent accuracy 1. for coding (UVM, systemverilog) as there are predefined set of keywords, classes, functions etc. 2. for GUI tool controls An example of coding: to see in editor "class myenv extends uvm_env;" I would Say: "class" type: myenv Say:"extends uvm_env;" For GUI usage, tool vendors/users could come up with a number of useful features similar to keyboard shortcuts. These features may be implemented both on Windows and Linux platforms. (Hope in few years engineers are able to dictate their code into a tool and debug it too! Also wish there is research on use of various HCIs for EDA) Thanks for reading my request! Regards, Kal Gandikota P.S.: I used windows speech recognition to write this e-mail as I am suffering from wrist pain. Please kindly ignore grammar mistakes.
  17. Hello all, How would one go about leveraging UVM for ES level DUT verification? Most of the stuff from RTL still applies but how do we correctly use the driver and monitor if the DUT does not have signals, but has TLM ports/sockets. The UVM states that one agent should be used per interface, but the problem on the ESL is that there are no signals so how do we monitor TLM ports/sockets with the monitor, while the driver stimulates the DUT? How do we connect ports/exports to the driver, monitor and the DUT simultaneously? A solution without using analysis ports would be great. I've included an image for easier reference. I guess that on ES level the monitor and driver are redundant, but then the sequencer would have to send packets to a checker and the DUT simultaneously, which would require either two ports or an analysis port. Another option would be to keep everything the same as in the image and have two ports, one from the driver to the DUT, and one from the driver to the monitor and send packets simultaneously. Please state your thoughts on this.
  18. Hi there A register can have different RTL implementation based on access_mode. ie., When a register REG_1 is read in backdoor, actual HDLPATH of the register would point to 'top.abc.dout'. When a register REG_1 is written in backdoor, actual HDLPATH of the register would point to 'top.abc.dout_temp' We want to program different hdlpaths to REG_1 based on access mode (READ or WRITE). Does UVM_REG provide ready-made hookups or methods like add_hdl_path_slice() methods to setup different hdlpaths to READ/WRITE backdoor access? (Inside the DPI based backdoor access itself?) I checked that write_backdoor and read_backdoor methods need to be overwritten to setup different HDLPATHs based on READ/WRITE access modes. But this involves overriding string based DPI backdoor access factory methods. I'm looking for an alternative here, if it really exists. Suggestions to this requirement, very much appreciated. Best regards Balasubramanian G
  19. Hi there We want to traverse through all registers present in a UVM_REG_BLOCK based on increasing address. We have the following pseudocode: model.NTB_DB.get_registers(total_regs_ntb); foreach (total_regs_ntb) begin total_regs_btb.write(status, wdata, .parent(this)); end But, the above source code does not go through the registers space based on address. ie., When I have a 2-dimensional array of registers, array indices are chosen first(not addresses). Any help to workaround this problem is appreciated. Best regards Balasubramanian G
  20. Hi, When I use the automation of register model by register assistant, in the video, it use the command 'vreguvm - gui' to translate the .csv file to register package. But When I input this command, it reminds me 'command not found'. what's the reason of that? The version I use is 10.2c_2. Do I need to install some package? If need, please tell me. I will ask the CAD administrator in my company to install it. And where can I get the csv templates mentioned in the mentor's video? Thanks
  21. I don't know if I'm posting in the right forum section, so I apologize in advance. I have a couple of questions about the UVM-ML architecture. For reference, I will be using the sc-sv unified hierarchy example, which is provided with UVM-ML-1.4.2. 1) In the sctop.cpp file, which looks like this: #include "uvm_ml.h" #include "ml_tlm2.h" #include "producer.h" #include "consumer.h" using namespace uvm; using namespace uvm_ml; // The environment component contains a producer and a consumer class env : public uvm_component { public: producer prod; consumer cons; env(sc_module_name nm) : uvm_component(nm) , prod("prod") , cons("cons") { cout << "SC env::env name= " << this->name() << endl; } void before_end_of_elaboration() { cout << "SC env::before_end_of_elaboration " << this->name() << endl; std::string full_initiator_b_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, tlm_generic_payload, b_isocket , 32); cout << "SC env registered " << full_initiator_b_socket_name << endl; std::string full_initiator_nb_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, tlm_generic_payload, nb_isocket , 32); cout << "SC env registered " << full_initiator_nb_socket_name << endl; std::string full_target_socket_name = ML_TLM2_REGISTER_TARGET(cons, tlm_generic_payload, tsocket , 32); cout << "SC env registered " << full_target_socket_name << endl; } ... UVM_COMPONENT_UTILS(env) }; UVM_COMPONENT_REGISTER(env) // Top level component instantiates env class sctop : public uvm_component { public: env sc_env; sctop(sc_module_name nm) : uvm_component(nm) , sc_env("sc_env") { cout << "SC sctop::sctop name= " << this->name() << " type= " << this->get_type_name() << endl; } ... UVM_COMPONENT_UTILS(sctop) }; UVM_COMPONENT_REGISTER(sctop) #ifdef NC_SYSTEMC NCSC_MODULE_EXPORT(sctop) #else int sc_main(int argc, char** argv) { return 0; } UVM_ML_MODULE_EXPORT(sctop) #endif What is the NC_SYSTEMC define and where is it used? What is UVM_ML_MODULE_EXPORT() and when is it used? 2) In file test.sv: import uvm_pkg::*; `include "uvm_macros.svh" import uvm_ml::*; `include "producer.sv" `include "consumer.sv" ... // Test instantiates the "env" and "testbench" which has a foreign child class test extends uvm_env; env sv_env; testbench tb; ... task run_phase(uvm_phase phase); `uvm_info(get_type_name(),$sformatf("SV test::%s %s", phase.get_name(), get_full_name()),UVM_LOW); while (1) begin #1 uvm_ml::synchronize(); end endtask ... `uvm_component_utils(test) endclass What is the uvm_ml::synchronize() function and when is appropriate to use it? If there are documents where I can find out more please mention them.
  22. Hi, While running simulation , i am getting the below mentioned error . Can anyone help me to fix this error. ncsim: *E,IMPDLL: Unable to load the implicit shared object. OSDLERROR: /prj/.../v/_sv_export.so: failed to map segment from shared object: Operation not permitted. ncsim: *W,LIBRUN: Could not load the dynamic library: ./INCA_libs/irun.lnx86.13.10.nc/librun System ERROR: ./INCA_libs/irun.lnx86.13.10.nc/librun.so: failed to map segment from shared object: Operation not permitted. ncsim: *F,NOFDPI: Function main not found in any of the shared object specified with -SV_LIB switchncsim: *E,IMPDLL: Unable to load the implicit shared object. Thanks Sidharth
  23. Mediatek is looking for verification engineers who are users of SV/UVM for their Bangalore center. Engineers in the experience range from 2-12 years can apply. If interested please send mail to ron.mediatek@gmail.com Essential Skills: Should have worked on at least one ASIC tapeout Hands on with SV/OVM/VMM/UVM Should have executed test planning at block/SoC level
  24. Hi there From the UVM users guide, a register read access can be executed as reg_model.BLK1.REG_FILE1.REG_1.read(status, rdata); But this mandates us to know the hierarchy of the register instantiation. ie., 'reg_model.BLK1.REG_FILE1' needs to be known to execute a read on register 'REG_1'. Is it possible to perform read/write access based on address instead of this hierarchy? Something like: generic_uvm_read (.address(0x0), rdata); In otherwords, we need not even know the register type or register instantiation hierarchy to issue a read access to that register. Can this be performed with UVM_REG? Requesting thoughts here. Best regards Balasubramanian G
  25. This is a online training batch taught by experts working in Semiconductor Industry. Course schedule is for 2.5 hours on Sat and Sun for 7 weeks. Graduates and working professionals can benefit from this training. For more details please email vlsitraining@sumerusolutions.com
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