Jump to content

Search the Community

Showing results for tags 'UVM'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus Pre-Release Discussion
    • Portable Stimulus 1.0
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 73 results

  1. Hi there IPXACT needs to capture array of registers properly in a design. Currently there is only one tag ''spirit:dim" to represent an array of registers. This does not enable us to capture an array of register effectively. Consider the following cases: 1. An array of registers can be one dimensional with each element offset by offset address 0x10. 2. An Array of multidimensional registers something like this: register_1[0][0] -> 0x0 register_1[0][1] -> 0x4 register_1[1][0] -> 0x10 register_1[1][1] -> 0x14 ... likewise Is there any way to capture just the address relationship to an array instance within IP-XACT XML tags? (Without using vendorExtensions tag?) We have not been able to capture the above said information inside IPXACT XML.(using only IP-XACT tags) Requesting thoughts regarding the same. Best regards Balasubramanian G
  2. Dear all, As we close in on delivering UVM 1.2 to the engineering community now is the time for you to read the docs, review the code, test the functionality. Or as they say forever hold your peace..... Once approved changing documentation requires another full review so really please do give your feedback ASAP. As a UVM user it is in your interest that UVM meets your requirements and your opinion is considered. There is a list of issues we know about within the Mantis database: http://www.eda.org/svdb/my_view_page.php If you want to view the code for a particular branch from sourceforge you can do so from your browser. http://sourceforge.net/p/uvm/code/ref/master/branches/ On the left click ""More Branches" UVM 1.2 will be built from the UVM_1_2 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2/tree/ At the time of writing the latest HTML docs are generated from RC4 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2_RELEASE_RC4_WITHHTMLDOC/tree/ It is just as easy to grab the latest code for you to run with your own projects for testing. A simple script can look like: #!/bin/csh -f mkdir $1; cd $1 ; git clone git://git.code.sf.net/p/uvm/code ; cd code ; git branch --track $1 origin/$1 ; git checkout $1 ; By passing in your branch name to the script it will checkout that particular branch for you. git_uvm.csh UVM_1_2 ; You can give feedback via your Accellera representation or local EDA person or provide feedback here. Time is of the essence so act today. thanks,
  3. Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog
  4. anupam

    UVM Register Model Generator

    Version 5.0


    This download contains a sample UVM environment that shows the use of IDesignSpec Free to generate a UVM Register Model. The input can be SystemRDL, IP-XACT, Word, Excel, XML etc. You can download the Free IDesignSpec Register Generator from here. You can use the included example as a ready reference to generate your own register model. You can use any or all of the IDesignSpec flavors: Word, Excel or Batch.
  5. hi, all, I'm a newer in learning UVM. With the support of many UVM experts, we can find many examples for learnning UVM. However, when I tried to have a taste on some examples using VCS to compile them, the Makefile is a headache for me. Could you please let me know how to write a good Makefile for compilation and running simulation in VCS? Thank you in advance! Liya
  6. I am learning UVM. So far I was able to create the following environment for my DUT. Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT. A top level UVM env. Sequences to send valid data to DUT. I yet to implement scoreboard. I'm having some trouble to understand how to handle scenarios like following: For one of my tb->dut interfaces, TB needs to wait for an event (or transaction) from DUT. Once it receives the transaction from DUT, TB needs to send back a response. What is the best way to implement this? How can I monitor DUT transaction from sequence? I assume I need to wait for an event or something similar which will tell me that DUT has a new valid output in its interface. My agents have monitors which will monitor any new output signals from DUT. So, do I need to somehow bring this data from agent's monitor to my test/sequence class? I know that monitor has an analysis port and it can be used to send received data to scoreboard for checking. So, do I need to use the same port to read DUT output data, create valid response and send it to DUT? Thanks!
  7. Event: Experiences of Using UVM - DVClub Shanghai Date: 28 March 2014 Time: 14.40 to 17.30 (CST) 07.00 to 09.30 (GMT) Organizer: Mike Bartley @TVS Roman Wang @AMD Charles Sun @Topbrian Sponsors: ARM, Cadence, Mentor and Synopsys The next DVClub Shanghai webcast event takes place on Friday, 28th March and will focus on the experience of UVM! Why not register to hear five speakers bringing their own unique perspective: Agenda (CST) 14.40 Arrival and Networking 15.00 Mike Bartley, Test and Verification Solutions - Verification Challange Outlook in 2014 15.30 Uwe Simm, Cadence - UVM1.2: What's Now and What's Next? 16.00 Yuanpeng Su, Synopsys - UVM Best Practices and Debug 16.30 Albert Chiang, Mentor Graphics - UVM, The Next Phase 17.00 Roman Wang, AMD - Are you Suffering to Handle on-the fly Events in Complex UVM Scenarios? 17.30 Close Registration and additional details of the presentations and speakers can be found here https://www.eventbrite.co.uk/e/dvclub-shanghai-28-march-2014-tickets-10200850017 Register the remote way if you could not access locally. DVClub Shanghai is organized by TVS & Topbrain who are committed to making DVClub Shanghai accessible to everyone and you can join the meeting remotely via the Internet or physically in shanghai. If you attend remotely why not do what many other companies do - book a room and invite your colleagues along so you can discuss and debate the topic.
  8. UVM doesn't have to be serious all the time, does it? fyi... we got a new dog to keep us company in the office. His name is uvm. He's a good dog. He does tricks, but he can't jump. www.realityreused.com/support.html -neil
  9. Hi all, What exactly is the difference between uvm_hdl_force and uvm_hdl_deposit? The UVM Class reference document doesn't provide much explanation. Please help. Thanks, Shreyas
  10. Hany Salah

    UVM in Questasim

    Can anyone here recommend me chapters needed to read in questasim user guide so as to simulate uvm systemverilog environment ,, let's have assumption that I have no knowledge about simulator commands interface ,,, thanks in advance
  11. What is the difference between configuration object and configuration space in UVM?
  12. Why the one need to set rand variables in configuration classes ,,, my knowledge is that Virtual Sequencer is the only component whose responsibility to generate random variables, isn't it ?
  13. Hany Salah

    Inquiry in UVM

    SA... the following lines are extracted from UVM user manual : class get_consumer extends uvm_component; uvm_blocking_get_port #(simple_trans) get_port; // the first line is understood to be class declaration as extension from uvm_component class. // I can't understand the 2nd line ,, could anyone here help me ?
  14. Hi, I'm using IUS 12.20.004 and trying to probe the UVM hierarchy for post processing in Simvision. Is it possible to probe variables of a task or function which is inside a class? I followed this guide: http://www.cadence.com/rl/resources/white_papers/post_process_uvm_wp.pdf I'm able to see data members of a class (the test class for example), but if there's a task or function inside the class, it isn't probed so I can't see its variables in the waves. Thanks, Eli
  15. Hi Guys, I am using UVM Register model to mimmick RTL's register implementation. Some registers are not implemented in RTL which are going to be connected to output port of some other module. I have got a HDL path of register as an output port declaration of some module. Something like: The HDL path is: "tb_top.dut_u.interrupt_module_u.o_ext_interrupt" o_ext_interrupt is declared as output port inside interrupt_module, which is not connected to any other wire or register. Can this output port's value be changed by writing to it via UVM BACKDOOR ? I am using following API: register_name.write(status,data,UVM_BACKDOOR,default_map); I dont see any change in value in the register. I think it is happening because the destination (o_ext_interrupt) is output of the module. I am using Cadence's simulator: irun. Please help if anyone is aware of such issue. Regards, Vismay.
  16. Hi, I have a interface monitor where i am capturing data from the interface. I need to pass valid data captured from the interface to the scoreboard for comparison. But the behaviour of interface signals and the way they are asserted depends on the register configuration. Now this config info is not known to the interface or the interface monitor. So while implementing the monitor, should i define two monitors 1) interface monitor which just samples all the data from the bus. 2) process data got in 1) furthur depending on the register config & then pass it on the scoreboard for comparison. Also should this be done using analysis ports? I think this is the right way but wanted to know if there is anything that UVM recommends in such cases. Thanks in advance. Parag
  17. In my earlier UVM days I ran into this confusing error message a number of times. I just hit it again, so am posting my solution here, to share and to help myself rediscover when it is time. Error (running IUS 13.1): uvm_analysis_imp_my_snoop #( xyz_trans, my_scoreboard) my_snoop_port; | ncvlog: *E,EXPENC (/user/goblin_dev/tb/my_scoreboard.svh,60|50): Expecting the keyword 'endclass'. Below is the pseudo code w/o the error. In converting the real code to pseudo code (to make it more succinct and sterilized), I do not believe I created any inconsistencies, but this is not what was compiled, of course. `uvm_analysis_imp_decl(_my_snoop) class my_scoreboard extends uvm_scoreboard; `uvm_component_utils(my_scoreboard) uvm_analysis_imp_my_snoop #( xyz_trans, my_scoreboard) my_snoop_port; function void build_phase(uvm_phase phase) my_snoop_port = new("my_snoop_port",this); endfunction : build_phase function void write_my_snoop( xyz_trans t ); //guts here endfunction : write_my_snoop endclass : my_scoreboard The error occurred when the following line was missing from above. `uvm_analysis_imp_decl(_my_snoop) So, without this macro called, the uvm_analysis_imp_my_snoop class is not declared. So, I would think that the error message would instead say that the class was not found. (I should try removing some random class that my tb needs and see what error message appears - b/c that is the error message I would expect here as well.) Appendix: The following code is taken from uvm-1.1/uvm_lib/uvm_sv/src/macros/uvm_tlm_defines.svh : // MACRO: `uvm_analysis_imp_decl // //| `uvm_analysis_imp_decl(SFX) // // Define the class uvm_analysis_impSFX for providing an analysis // implementation. ~SFX~ is the suffix for the new class type. The analysis // implemenation is the write function. The `uvm_analysis_imp_decl allows // for a scoreboard (or other analysis component) to support input from many // places. For example: // //| `uvm_analysis_imp_decl(_ingress) //| `uvm_analysis_imp_decl(_egress) //| //| class myscoreboard extends uvm_component; //| uvm_analysis_imp_ingress#(mydata, myscoreboard) ingress; //| uvm_analysis_imp_egress#(mydata, myscoreboard) egress; //| mydata ingress_list[$]; //| ... //| //| function new(string name, uvm_component parent); //| super.new(name,parent); //| ingress = new("ingress", this); //| egress = new("egress", this); //| endfunction //| //| function void write_ingress(mydata t); //| ingress_list.push_back(t); //| endfunction //| //| function void write_egress(mydata t); //| find_match_in_ingress_list(t); //| endfunction //| //| function void find_match_in_ingress_list(mydata t); //| //implement scoreboarding for this particular dut //| ... //| endfunction //| endclass `define uvm_analysis_imp_decl(SFX) \ class uvm_analysis_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_ANALYSIS_MASK,`"uvm_analysis_imp``SFX`",IMP) \ function void write( input T t); \ m_imp.write``SFX( t); \ endfunction \ \ endclass
  18. I've run into the following issue using the built-in UVM register tests. The built-in UVM register tests (seem to) start R/W-ing immediately after top-level reset is released. This was fine, initially. See attached image "Capture". We now have some delay between the release of top-level reset and the actual reset going to the register block. This is resulting in a read occurring before reset to the rtl regblock is released, and causes the test to hang. See attached image "Capture2". Without modifying the built-in register tests/sequences, how would anyone suggest that we cleanly delay the stimulus? Perhaps I just need to make the stimulus aware of the different reset when the model/stimulus is generated, or simple add some delay to a phase before the R/W-ing starts. (The former sounds right. If that's the solution, I'll need to figure out how we're generating the model/stimulus.) I've just started hunting around for the built-in UVM register test sequences and will return to it tomorrow, but will anyone tip me off as to what names I should be searching for? thanks This has been useful, https://verificationacademy.com/cookbook/registers/builtinsequences, but it seems I need to do some more reading and hunting before I grasp how the built-in register stimulus is created and used.
  19. Not sure do you have similar problem? I have a problem in handling the reset value in RAL. f the reset value of a field in the register is don't care, what can I do for it? Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked. Do you guys think it is a feasible way? Thanks.
  20. One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun. ) =Adam Sherilog, Cadence
  21. Doulos will be running a webinar on Friday 26th April "The Finer Points of UVM Sequences". Presented by John Aynsley, Doulos CTO Register here! http://www.doulos.com/content/events/easierUVM_The_Finer_Points.php
  22. Hi I am new to UVM. Can any one provide the sample example for using uvm_post_main_phase? Thanks, Ravi
  23. Dear SystemVerilog/UVM User, I've setup a SystemVerilog Meetup in Silicon Valley for people who are interested in hashing over problems they're having or learning new features in a group setting. http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley/ I look forward to seeing you there. all the best, Linc Jepson