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Hans64

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  1. Like
    Hans64 got a reaction from Philipp A Hartmann in sc_signal concatenation   
    Hi Sachin,
     
    For concatenation one of the arguments should be a vector.
     
     
    This will fail as all the arguments are sc_logic.
     
    See LRM section 7.2.7
     
    Regards,
    Hans.
    www.ht-lab.com
  2. Like
    Hans64 got a reaction from Annossyenudge in IO port by reference   
    Hi All,

    Can I pass a reference to IO port?

    The code below results in a Modelsim error which I suspect is because of the sc_out reference
     
    SC_MODULE(PROC3) { sc_in<bool > clk; sc_in<bool > reset; sc_in<bool > dbusin; sc_out<bool > dbusout; void doff(const sc_core::sc_in<bool>pin, sc_core::sc_out<bool>&pout) { pout.write(pin.read()); } void entry_clk() { while(true) { doff(dbusin,dbusout); wait(); } } SC_CTOR(PROC3) { SC_CTHREAD(entry_clk,clk.pos()); } };
    # ** Error: (vsim-6511) Insert port failed: simulation running: port '/proc3_tb/DUT/entry_clk/port_0' (sc_port_base)
    # In process: /proc3_tb/DUT/entry_clk @ 55 ns


    Thanks,
    Hans.
  3. Like
    Hans64 got a reaction from foster911 in Verification Methodologies for SystemC   
    Yes, AVM is still supported by Questa.
     
    AVM is not the only Verification Framework, there is also Cadence's UVM multi-language package. It is not a full SystemC UVM implementation as assertions and the sequencer still requires SVA/SystemVerilog.
     
    Hans
    http://www.ht-lab.com
  4. Like
    Hans64 got a reaction from mohitnegi in data structure with link list   
    Hi Mohit,
     
    This is described in section 9.4 of the SystemC Synthesizable Subset document:
     
     
    Both Fossy and Vivado do not support SC_THREAD, not sure about the high-end Mentor's Catapult-C and Forte Cynthesizer which might support some constructs.
     
    Regarding Dynamic Sensitivity, everytime you see the word Dynamic think about how this would translate to hardware. Leaving Dynamic Reconfigurable Hardware to one side in general everything you code must be static.
     
    Regards,
    Hans.
    http://www.ht-lab.com
  5. Like
    Hans64 got a reaction from mohitnegi in data structure with link list   
    AFAIK for synthesis you need to stick to fixed size arrays. I would suggest you read up what memory templates vendors recommend before you start coding. You can read the synthesis guides for Vivado, Fossy and probably some others on the web.  Be prepared to instantiate some VHDL/Verilog code if you need more complex multi port memory models.

    Good luck,

    Hans.
    www.ht-lab.com
  6. Like
    Hans64 got a reaction from maehne in SystemC / SystemC TLM Verification   
    There is a SystemC VMM class library (VMM came before OVM which came before UVM which will probably be replaced again soon by another acronym .....)
    I believe SCV is still being looked at but constraint solvers are complex pieces of technology combine this with non-perfect C++ introspection and you have a complex task at hand.
    From what I have heard Cadence continues to maintain and update SCV commercially (for NCsim), so what we need is for some of their engineers to have a look at the current SCV version and bring it back to live ;-)
    Hans.
    www.ht-lab.com
    PS I would not compare UVM with SCV as they are quite different. UVM is a Verification framework whereas SCV is more of a verification toolbox.
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