Jump to content

Hans64

Members
  • Content Count

    33
  • Joined

  • Last visited

  • Days Won

    3

Everything posted by Hans64

  1. Modelsim (and most likely all other commercial simulation) provide a conversion utility to convert VCD to their own format. For Modelsim this is vcd2wlf, convert both files to the wlf format then use Modelsim's filecompare to do the comparison (with all the available bells and whistles which you may need). You can quite easily script this up and add it to a GUI button. Good luck, Hans. www.ht-lab.com
  2. I agree, however I wouldn't underestimate the number of Windows SystemC users. I did do a quick port to Linux (CentOS7) but after some strange build issues I shelved it and will look at it again at a later date. I like Visual Studio as well and use it to build SCBuilder. However, SCBuilder is more aiming to be like a light version of Vivado, it is unlikely somebody will write a Tcl engine or add synthesize capability in a Visual Studio plugin. These are all good point and a static linting tool is on my todo list. Some other feedback I received from the website, the download file is too large. yes, and I am afraid it is only getting larger. I could make installing TDM-GCC-32 and the libraries optional but this will add complications for the GUI. Make source code available, perhaps in the future. Printing is not working, confirmed. "IC button" not working, this is part of the synthesis capability which I will hopefully add this weekend. Word selection is not working, it took me some time to understand this, confirmed. User configurable shortcuts, on my todo list, Crashes frequently on Win8, I do not have access to Win8 but on Win7/10 it seems stable. Linux version in source, perhaps in the future. Emacs editor plugin, perhaps in the future. Thanks for the feedback, Hans www.ht-lab.com
  3. Hi all, I have written a simple Windows SystemC IDE called SCBuilder. http://www.ht-lab.com/scbuilder.htm The basic idea is to have a dedicated SystemC IDE which allows the user to create SystemC/SCV/UVM programs with a minimum of fuss. The user can simply drag and drop files into a project and compile/debug/run the program with a click of a button (thanks to the power of CMake). Other features are a build-in VCD viewer and Tcl scripting capability. The compiler is based on the latest tdm-gcc (gcc 5.1.0). Upcoming features are (basic) synthesis and code coverage, I would appreciate any feedback on this alpha version, Thanks, Hans. www.ht-lab.com
  4. Hi Stephan, I am not sure you have to specify the bit width for real's as the format seems to be fixed to double precision. Also you cannot dump part of a vector so the bit width is redundant. This is what I picked up from the LRM: A real number is dumped using a %.16g printf() format. This preserves the precision of that number by outputting all 53 bits in the mantissa of a 64-bit IEEE Std 754-1985 [b1] double-precision number. Application programs can read a real number using a %g format to scanf(). I might be wrong of couse, you could raise an SR with Mentor to see what they have to say, Good luck, Hans.
  5. Hi Mike, You are correct (I was wrong) for some reason OSCI puts everything under the same (SystemC) scope. You can use your utility or patch OSCI (have not tried it myself): https://github.com/yTakatsukasa/misc/tree/master/systemc-2.3_vcd_hier Regards, Hans.
  6. Hi Mike, The dot notation should work, I would suggest you have a look at your vcd file to see if the hierarchy is recorded, you should see something like: sc_trace(fp,top.u1.signalx,"signalx"); $scope module top $end $scope module u1 $end $var wire 1 ^ signalx $end $upscope $end $upscope $end good luck, Hans.
  7. Hi Jintao, You can change the Modelsim SystemC stacksize by modifying the ScMainStackSize variable in your modelsim.ini file. I believe there is also a SystemC set_stack_size() call you can use. Good luck, Hans. www.ht-lab.com
  8. The easiest way would be to get a SystemC license for your Modelsim. If this is not possible then there are the usual methods for interprocess communication. Probably the easiest method is to use sockets, you could use Tcl (force/when/examine) to modify your VHDL. If you have Modelsim DE then you can use the FLI (VHDL C/C++) interface again with sockets (there are FLI sockets function). If you are under Linux you can try named pipes (I failed to make it work under Windows) and of course you could use simple text files, Good luck! Hans www.ht-lab.com
  9. Hi Martin, This is quite interesting as I am sure a free UVM implementation is not something the Vendors (paying Accellera members) are looking forward to. Interesting project, Regards, Hans www.ht-lab.com
  10. Perhaps a good old union can help you out: union float_int32 { float f; uint32_t i; }; float_int32 fl; fl.f=0.1234; // result fl.i=03dfcb924 Good luck, Hans. www.ht-lab.com
  11. Hi Sachin, For concatenation one of the arguments should be a vector. This will fail as all the arguments are sc_logic. See LRM section 7.2.7 Regards, Hans. www.ht-lab.com
  12. I don't believe there is any elegant solution other than changing your U1.I1 input port to type bool or write a separate clock module. In addition to dakupoto answers you can also: sc_l = static_cast<sc_logic> (bb); bb = sc_l.to_bool(); Resolution between 'X'/'Z' and '0'/'1' will not be the same as in VHDL. Good luck, Hans. http://www.ht-lab.com
  13. ~ is a perfectly legal operator for sc_logic, see the LRM. The problem was the OP was using an implicit method call which confused the compiler. Changing to an explicit .read() method call should fix the problem. Regards, Hans.
  14. Try: void proc() { o.write(~a.read()); } Hans.
  15. Something must be wrong in your setup, do any other SystemC programs work? What is the error message? All bitwise operators (& ! ^ ~) should work for sc_logic. You can also use the logical ! after converting it to boolean (.to_bool()). Hans.
  16. Use the bitwise operator ~ Hans.
  17. Sorry, was in a rush yesterday. Just add simstats cpu (or just simstats) to the end of your simulation script and Questa will give you a bunch of statistics including the time vsimk (the simulation kernel) runs. vsim -c -do "run -all; simstats" top-level-module" See the command reference manual for more info. Regards, Hans. www.ht-lab.com
  18. I would suggest you also try 64bits Linux as I assume you are using gcc under Mingw-w64 which is still considered somewhat unstable. Good luck, Hans www.ht-lab.com
  19. Yes, AVM is still supported by Questa. AVM is not the only Verification Framework, there is also Cadence's UVM multi-language package. It is not a full SystemC UVM implementation as assertions and the sequencer still requires SVA/SystemVerilog. Hans http://www.ht-lab.com
  20. Hi Sumit, I agree that VCD is past it sell by date but don't forget that OSCI is just a reference design, it is not a commercial product. All commercial SystemC simulators come with a wide range of debugging and logging capabilities including TLM and Analog. I don't think Accellera will have much interest in improving the VCD capabilities especially when there are other more urgent area's (like SCV, SC-UVM) that needs attention. They also don't want to make OSCI to powerful/capable as this could impact commercial offerings. Regards, Hans. www.ht-lab.com
  21. Hi Mohit, This is described in section 9.4 of the SystemC Synthesizable Subset document: Both Fossy and Vivado do not support SC_THREAD, not sure about the high-end Mentor's Catapult-C and Forte Cynthesizer which might support some constructs. Regarding Dynamic Sensitivity, everytime you see the word Dynamic think about how this would translate to hardware. Leaving Dynamic Reconfigurable Hardware to one side in general everything you code must be static. Regards, Hans. http://www.ht-lab.com
  22. AFAIK for synthesis you need to stick to fixed size arrays. I would suggest you read up what memory templates vendors recommend before you start coding. You can read the synthesis guides for Vivado, Fossy and probably some others on the web. Be prepared to instantiate some VHDL/Verilog code if you need more complex multi port memory models. Good luck, Hans. www.ht-lab.com
  23. Hi Mohit, See, http://www.accellera.org/activities/committees/systemc-synthesis/ http://en.wikipedia.org/wiki/Electronic_system-level_design_and_verification HLS is High Level Synthesis, Hans. www.ht-lab.com
  24. Hi Mohit, See, http://www.accellera.org/activities/committees/systemc-synthesis/ http://en.wikipedia.org/wiki/Electronic_system-level_design_and_verification HLS is High Level Synthesis, Hans. www.ht-lab.com
×
×
  • Create New...