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StS last won the day on December 11 2017

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  1. Hi Kevin, you are missing the raising and dropping of an objection in the run_phase method (which would be required in SystemVerilog too) to prevent the early finish of the test sequence: void run_phase(uvm::uvm_phase& phase) { phase.raise_objection(this); [...] phase.drop_objection(this); } By adding this I get the desired result: UVM_INFO @ 0 s: reporter [RNTST] Running test ... run: before fork/join Current time is 0 s =========== fun1======== Current time is 0 s =========== fun2======== Current time is 20 ns run: after fork/join Current time is 60 ns UVM_INFO ../../../../uvm-systemc-1.0-beta2/src/uvmsc/report/uvm_default_report_server.cpp(666) @ 60 ns: reporter [UVM/REPORT/SERVER] --- UVM Report Summary --- ** Report counts by severity UVM_INFO : 1 UVM_WARNING : 0 UVM_ERROR : 0 UVM_FATAL : 0 ** Report counts by id [RNTST] 1 UVM_INFO @ 60 ns: reporter [FINISH] UVM-SystemC phasing completed; simulation finished
  2. StS


    I assume that by this term an empty verification IP is meant. So you would have just to fill in specific functionality such as e.g. the driver interface, monitor interface, items, sequences, etc.
  3. Hi! This actually depends on how you implemented your agent and how you implemented its configuration abilities. This is more a general UVM design question and not strongly UVM-SystemC related.
  4. StS

    CRAVE versus SCV

    Hi all, SCV is considered now in maintencance mode. This means we will adapt it to issues with new compilers and build flows but we will not add new features. Currently we are focussing our effort on UVM-SystemC. Best, Stephan
  5. It seems that a forgotten comment in file src/uvmsc/factory/uvm_default_factory.cpp line 1044 seems to be the culprit. Only printing should be affected. However, we will check within the workgroup if other effects are to be expected. For now, changing if( !m_type_overrides.size() ) //&& !sorted_override_queues.size() ) to if( !m_type_overrides.size() && !sorted_override_queues.size() ) should solve your issue.
  6. Can you provide your whole command line for building SystemC & UVM-SystemC and your example?
  7. Hi! the missing configure script will be included in the next release. CMake build is not completely supported yet but is now on our bug tracker. Thank you for reporting!
  8. This is a known limitation, we ran into this issue last year too. If you look closely you will find commented macros in the scv_extensions mentioning sc_fixed and sc_ufixed. However, uncommenting these entry will not work as these seem to be leftovers from the early implementation dating back to around 2000 when first commits were publicly recorded. You will probably have to find a workaround for that at the moment. Adapting the scv_extensions does not look too trivial.
  9. What kind of problems do you run into? Basically you have to build the SCV library first. After that you can compile the examples via "g++ *.cc -L<scv_install_dir> -lscv -o example".
  10. There is an internal buglist for the developers but AFAIK this bug is not known yet. The minimal example would help alot figuring it out.
  11. Hi! We have now released an updated version of SCV which should fix this issue for you.. You can find it here: http://accellera.org/downloads/standards/systemc
  12. Hi! as in the previous alpha release you should call config/bootstrap beforehand. This will create a configure script for you. (This is mentioned in the INSTALL file around line 226.)
  13. We are working on releasing an compatibility update rather soon, probably this year.
  14. Hi Aixeta, this is already fixed in the upcoming release of the SCV. Meanwhile you can workaround by casting directly to sc_logic: sc_dt::sc_logic_value_t(this->_get_instance()->get_bit(i))
  15. Hi Frank, thanks for reporting, I've implemented a patch following Torstens recommendation in the working groups repository. This will be included in the next release which will be alongside SystemC 2.3.2.