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WangYuchen

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  1. Hello all, I met a general problem when I was running simulation on SystemC platform. Maybe it not a problem, but I would like to figure out how it comes. Info (OR_OF) Target 'ram_sh' has object file read from '../../Loader_Scheduler/program_examples/test.MIPS32.elf' Info (OR_SH) Section flg sect addr size load addr file offset Info (OR_SD) .text -ax 0x80080000 0x00005920 0x80080000 0x00000058 Info (OR_SD) .init -ax 0x80085920 0x00000024 0x80085920 0x00005978 Info (OR_SD) .fini -ax 0x80085944 0x0000001c 0x80085944 0x0000599c Info (OR_SD) .rodata -a- 0x80085960 0x00000804 0x80085960 0x000059b8 Info (OR_SD) .sdeinit -a- 0x80086164 0x00000004 0x80086164 0x000061bc Info (OR_SD) .sdefini -a- 0x80086168 0x00000004 0x80086168 0x000061c0 Info (OR_SD) .sdeosabi -a- 0x8008616c 0x00000008 0x8008616c 0x000061c4 Info (OR_SD) .eh_frame -a- 0x80086174 0x00000044 0x80086174 0x000061cc Info (OR_SD) .data wa- 0x800861b8 0x000002d8 0x800861b8 0x00006210 Info (OR_SD) .ctors wa- 0x80086490 0x00000008 0x80086490 0x000064e8 Info (OR_SD) .dtors wa- 0x80086498 0x00000008 0x80086498 0x000064f0 Info (OR_SD) .jcr wa- 0x800864a0 0x00000004 0x800864a0 0x000064f8 Info (OR_SD) .sdata wa- 0x800864a4 0x00000018 0x800864a4 0x000064fc ======================= number is 0 number is 1 number is 2 number is 3 number is 4 number is 5 number is 6 number is 7 number is 8 number is 9 ======================= number is 0 number is 1 number is 2 number is 3 number is 4 number is 5 number is 6 number is 7 number is 8 number is 9 ======================= number is 0 number is 1 number is 2 number is 3 number is 4 number is 5 number is 6 number is 7 number is 8 number is 9 ======================= number is 0 number is 1 number is 2 number is 3 number is 4 number is 5 number is 6 number is 7 number is 8 number is 9 ------Start Loader_Scheduler------ Now is at0 s ------Finish Loader_Scheduler------ SystemC: simulation stopped by user. Finished simulation 1 Info Info --------------------------------------------------- Info CPU '/top.cpu_4' STATISTICS Info Type : mips32 Info Nominal MIPS : 100 Info Final program counter : 0x80080084 Info Simulated instructions: 8,700 Info Simulated MIPS : run too short for meaningful result Info --------------------------------------------------- Info Info --------------------------------------------------- Info CPU '/top.cpu_3' STATISTICS Info Type : mips32 Info Nominal MIPS : 100 Info Final program counter : 0x80080084 Info Simulated instructions: 8,700 Info Simulated MIPS : run too short for meaningful result Info --------------------------------------------------- Info Info --------------------------------------------------- Info CPU '/top.cpu_2' STATISTICS Info Type : mips32 Info Nominal MIPS : 100 Info Final program counter : 0x80080084 Info Simulated instructions: 8,700 Info Simulated MIPS : run too short for meaningful result Info --------------------------------------------------- Info Info --------------------------------------------------- Info CPU '/top.cpu_1' STATISTICS Info Type : mips32 Info Nominal MIPS : 100 Info Final program counter : 0x80080084 Info Simulated instructions: 8,743 Info Simulated MIPS : run too short for meaningful result Info --------------------------------------------------- Info Info --------------------------------------------------- Info TOTAL Info Simulated instructions: 34,843 Info Simulated MIPS : run too short for meaningful result Info --------------------------------------------------- Info Info --------------------------------------------------- Info SIMULATION TIME STATISTICS Info Simulated time : 0.00 seconds Info User time : 0.04 seconds Info System time : 0.01 seconds Info Elapsed time : 0.05 seconds Info --------------------------------------------------- CpuManager finished: Fri Oct 26 17:08:00 2012 After the 4 processors simulated, there is a stop "SystemC: simulation stopped by user". I was wondering if the unexpected stop is from platform or ELF linked file. I didn't use sc_stop() or setting the time for sc_start() (such as sc_start(20, SC_MS)). Thus, how the stopp comes? Is it because of the "return 0;" at the end of ELF file? Or, there is nothing to change in simulation environment?
  2. Thank you, Alan. I fully agree with what you said. To put the processor into idle loop and use an interrupt handler to trigger on. The body of source code I have given is just a general assumption... I already found the error of ERROR[113]. Because in loader_scheduler module, I made a terrible mistake that I defined hwint0-3 as sc_signal<> which were supposed to be sc_inout<>. That means, I didn't connect loader_scheduler to each MIPS processor. Thank you very much.
  3. Hello all, Here is my platform structure: 1. 4 MIPS processors have separated data memories ( "data0--data3" ) by separated buses ( "busd0-3" ) 2. 4 processors share the same program memory ( "program" ) by ("busp0-3" and "busp_sh") source codes of platform : program ("program", "sp1", 0x10000000), data0 ("data0", "sp1", 0x10000), data1 ("data1", "sp1", 0x10000), data2 ("data2", "sp1", 0x10000), data3 ("data3", "sp1", 0x10000), …… // busp_sh busp_sh.initiator_socket[0](program.sp1); busp_sh.setDecode(0, 0x0, 0xfffffff); // busp0 master cpu0.INSTRUCTION.socket(busp0.target_socket[0]); // busp0 slave busp0.initiator_socket[0](busp_sh.target_socket[0]);// Program Memory busp0.setDecode(0, 0x80080000, 0x8017ffff); // busp1 master cpu1.INSTRUCTION.socket(busp1.target_socket[0]); // busp1 slave busp1.initiator_socket[0](busp_sh.target_socket[1]);// Program Memory busp1.setDecode(0, 0x80180000, 0x8027ffff); // busp2 master cpu2.INSTRUCTION.socket(busp2.target_socket[0]); // busp2 slave busp2.initiator_socket[0](busp_sh.target_socket[2]);// Program Memory busp2.setDecode(0, 0x80280000, 0x8037ffff); // busp3 master cpu3.INSTRUCTION.socket(busp3.target_socket[0]); // busp3 slave busp3.initiator_socket[0](busp_sh.target_socket[3]);// Program Memory busp3.setDecode(0, 0x80380000, 0x8047ffff); // busd0 master cpu0.DATA.socket(busd0.target_socket[0]); // busd0 slave busd0.initiator_socket[0](data0.sp1); // Data Memory busd0.setDecode(0, 0x08000000, 0x0800ffff); // busd1 master cpu1.DATA.socket(busd1.target_socket[0]); // busd1 slave busd1.initiator_socket[0](data1.sp1); // Data Memory busd1.setDecode(0, 0x08010000, 0x0801ffff); // busd2 master cpu2.DATA.socket(busd2.target_socket[0]); // busd2 slave busd2.initiator_socket[0](data2.sp1); // Data Memory busd2.setDecode(0, 0x08020000, 0x0802ffff); // busd3 master cpu3.DATA.socket(busd3.target_socket[0]); // busd3 slave busd3.initiator_socket[0](data3.sp1); // Data Memory busd3.setDecode(0, 0x08030000, 0x0803ffff); …… int sc_main() { unsigned char *targetshPtr = top.program.getMemory()->get_mem_ptr(); top.cpu0.loadNativeMemory(targetshPtr, 0x10000, 0x80080000, "program", app, 0, 1, 1); } Here is the definition of "loadNativeMemory()": /// Load an object file into native memory. /// The native memory has been allocated by the user (it is not ICM memory), /// and has probably been mapped into this procesor's address space using /// the icmBusObject mapNativeMemory() method. /// This is available as a method on the processor object so that the code can /// be intercepted by any intercept library associated with this processor. /// @param nativeMemory Pointer to the (pre-allocated) native memory. /// @param roomInBytes Size of the allocated region (provided so the loader can detect /// and prevent overflow. /// @param base The physical bas of this memory in the processor address space. /// The base is subtracted from each load-address before loading. /// @param memoryName A name chosen for the memory. This is used by the loader /// when reporting errors. /// @param objectFile Path to the object file (currently ELF format only). /// @param loadPhysical If true, use the physical addresses from the object file /// (otherwise use the logical addresses). /// @param verbose If true, print a summary of the sections as they are loaded. /// @param useEntry If true, set the processor PC to the entry point void loadNativeMemory( void *nativeMemory, Uns64 roomInBytes, Uns64 base, const char *memoryName, const char *objectFile, Bool loadPhysical, Bool verbose, Bool useEntry ); The result of simulation shows that : Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/opt/comware/share/Imperas/Imperas32/Imperas.20120614/lib/Linux32/ImperasLib/mips.ovpworld.org/semihosting/mips32SDE/1.0/model.so' Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/opt/comware/share/Imperas/Imperas32/Imperas.20120614/lib/Linux32/ImperasLib/mips.ovpworld.org/processor/mips32/1.0/model.so' Info (OR_OF) Target 'program' has object file read from './program_examples/test.MIPS32.elf' Info (OR_SH) Section flg sect addr size load addr file offset Info (OR_SD) .text -ax 0x80080000 0x00005840 0x80080000 0x00000058 Info (OR_SD) .init -ax 0x80085840 0x00000024 0x80085840 0x00005898 Info (OR_SD) .fini -ax 0x80085864 0x0000001c 0x80085864 0x000058bc Info (OR_SD) .rodata -a- 0x80085880 0x000007f8 0x80085880 0x000058d8 Info (OR_SD) .sdeinit -a- 0x80086078 0x00000004 0x80086078 0x000060d0 Info (OR_SD) .sdefini -a- 0x8008607c 0x00000004 0x8008607c 0x000060d4 Info (OR_SD) .sdeosabi -a- 0x80086080 0x00000008 0x80086080 0x000060d8 Info (OR_SD) .eh_frame -a- 0x80086088 0x00000044 0x80086088 0x000060e0 Info (OR_SD) .data wa- 0x800860d0 0x000002d8 0x800860d0 0x00006128 Info (OR_SD) .ctors wa- 0x800863a8 0x00000008 0x800863a8 0x00006400 Info (OR_SD) .dtors wa- 0x800863b0 0x00000008 0x800863b0 0x00006408 Info (OR_SD) .jcr wa- 0x800863b8 0x00000004 0x800863b8 0x00006410 Info (OR_SD) .sdata wa- 0x800863bc 0x00000018 0x800863bc 0x00006414 Processor Exception (PC_PRX) Processor 'top.cpu0' 0x80080030: lw t0,25156(t0) Processor Exception (PC_RDX) Read abort at 0x80086244 In initialization, I separated all the decode ranges to get rid of overlapping. Read abort indicates there is no memory at the address being read. Could you give me any hits for this error? Thank you very much.
  4. Thank you, Philipps and David! Actually, I have finished all the Initialization in Constructor. such as: { loader_scheduler = new Loader_Scheduler("loader_scheduler"); // bind sockets for router and loader_scheduler cpu0.hwint0.write(loader_scheduler->hwint0); cpu1.hwint1.write(loader_scheduler->hwint1); cpu2.hwint2.write(loader_scheduler->hwint2); cpu3.hwint3.write(loader_scheduler->hwint3); ...... } In the loader_scheduler module: switch (count % 4) { case 0: memcpy ( ptr_data0_global, callback_result->packet, (int)(callback_result->header).len ); hwint0.write(true); hwint1.write(false); hwint2.write(false); hwint3.write(false); break; ...... } I don't think it create any new instances during simulation only by changing the value of sc_signal. Jump out of the creating new instances topic, let's thinking about the concept of this work: 1. first packet comes, load into Datamemory0 and trigger on Processor0 2. second packet comes, load into Datamemory1 and trigger on Processor1 (Procesor0 is still WORKING) ...... How can I achieve this target in the sc_main()? sc_main() is a kind of this structure: int sc_main (int argc, char *argv[] ) { const char *app; char* pcap_file; icmIgnoreMessage("ICM_NPF"); TopLevel_Mips32_TLM2_0 top("top"); //instantiate example top module // Allow different files to be loaded on command line if (argc > 1) { app = argv[1]; pcap_file = argv[2]; pcap_file_global = pcap_file; } // pass the data memory address for preloading ptr_data0_global=top.data0.getMemory()->get_mem_ptr(); ptr_data1_global=top.data1.getMemory()->get_mem_ptr(); ptr_data2_global=top.data2.getMemory()->get_mem_ptr(); ptr_data3_global=top.data3.getMemory()->get_mem_ptr(); // Use the TLM shared memory. It needs to be loaded with the program. unsigned char *targetshPtr = top.program.getMemory()->get_mem_ptr(); top.cpu0.loadNativeMemory(targetshPtr, 0x10000, 0x80080000, "program", app, 0, 1, 1); sc_core::sc_start(); // start the simulation cout << "Finished sc_main." << endl; return 0; // return okay status } Preloading finishes before sc_start, simulation starts after sc_start. How can I achieve multiple simulations which start at different timespots. Sorry for posting so many things. I have no idea how to build the body of codes ( sc_main() ), and I could assume "the Error: (E113) insert primitive channel failed: simulation running" could be solved if I have a more clear structure. Thank you very much.
  5. Hello all, I am going to build a four-MIPS platform by SystemC TLM2.0. The purpose for that platform: 1. capture pcap dump file and preload into data memory; 2. load OpenDPI program into program memory; 3. trigger the MIPS processor on and simulate the performance. I built a module called "Loader_Scheduler" which is used to capture packets in sequence and preload the data of each packet into different data memories. The whole story is like, capture first packet and run the MIPS simulation, in the meantime, "Loader_Scheduler" will capture the second packet. But I encountered such error: Error: (E113) insert primitive channel failed: simulation running In file: sc_prim_channel.cpp:166 In process: top.loader_scheduler.loader_scheduler @ 0 s Finished sc_main. I googled it: Error: (E113) insert primitive channel failed: simulation running In file: ../../../../src/sysc/communication/sc_prim_channel.cpp:166 Any of your module has attempted to create an instance of a primitive channel (sc_signal, sc_fifo, etc) after the start of simulation.In systemC primitive channels can only be created before the start of simulation . Please search your code for any signal declaration inside a function. Does it mean I cannot let Loader_Scheduler run after the simulation start? Could you provide me any suggestions to solve it by loop or something else? Thank you!
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