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bluephilosopher

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  1. Hey, recently I need to draw a flowchart of the systemC-TLM based codes. I tried to find out some standard icons for representing modules, interfaces, channels...I do find some in the book: SystemC: From the Ground Up 2nd Edition, on page xi. But its not that detailed. Any suggestion?
  2. hey Ralph thanks... sorry for the late reply... I have figured out the solution. I just changed the sc_method to sc_thread...I was reluctant to do it, just because of wait(). But since it´s working, so why not...
  3. then how about to wait for a certain time, but not a delta cycle? Should I then change the method3 to a sc_thread? ############################################ Why is the idea of let sc_method to run without delay? Does it represent any real hardware?
  4. I hope I have made the topic title understandable, jeje There is the question: I have a sc_method method1 with static sensitivity to 2 signals, sig_1 and sig_2. and sc_method method2 is sensitive to sig_1. When the sig_1 in simulator is changed, method1 is triggered by sig_1, and after a delta cycle, agian by sig_2. Is there a way to let the sensitivity of method1 to sig_1 wait for a delta cycle, i.e. ignore the sensitiviy of sig_1, if after a delta cycle there is the sensitiviy of sig_2 thanks sc_method(method1) sensitivity << sig_1 <<sig_2; sc_method(method2) sensitivity << sig_1; /* simulator */ sig_1.write(variable);
  5. Hey Rahlph, thanks for the explanation. Yes, you are right. That´s actually a hardware understanding.. I figured it with event and global variable, though it´s not a good solution, since the shared memory issue of global variables. but it works... thanks
  6. Hey Ralph, thanks. This really helps. The example is neat and easy to understand...I have not found the sc_find_event in my golden reference guide. ################################################## After rechecking my codes, I ran into another problem. I have a signal which is set to true in modules A and to false in module B. A process in module C is sensitive to the signal. For triggering the process in module C, I tried to use two buffers: set_sig and clear_sig, with either the sensitive list or event notification. Both work fine. Yet. I need to know the value of the signal for if-else calculation. The values of the two signals are actually the same. I tried to use the sc_signal_resolved, with which I only need a signal. Yet the value of the signal remains the same, i.e. "X" (A="0", B="1") Any suggestion?
  7. Hey Ralph, thanks. But as you said sc_event is not bound to anything. So it´s could only be applied in the same module/ sub module, right? The thing is, I have multiple modules instantiated in top. and between these modules I need to write to a shared memory. and there is one module which will read from this shared memory, i.e. module A/B/C/D, write to it, and module E read it. But for sc_signal, it´s not allowed. I´m considering to use sc_semaphore, but after reading some reference books, i could not find this cross module application examples. thanks
  8. Hey Ralph, thanks a lot. It works now. At the same time, I also found a similar example on cross hierarchy. Now I came to question of sc_event on cross hierarchy. I set the sc_event as the sc_signal like above. but it does not work. any suggestion?
  9. hey Hey Ralph, I have similar question: I have class father, it has different classes inside, son1, son2.but these classes have the same generic class definition, say class son then there is an another class, say, class mother now I want to use sc_method to run a function in class mother, which is sensitive to a variable called flag in class son...(i.e. there are actually two variables, in son1 and son2, but the definition of this variable is generic, which is in class son) What I did is to define like following: top: sc_signal<>flag son: sc_out<>flag mother: sc_in<>flag And for binding the signal, i did like this father1.son1.flag(flag) mother1.flag(flag) father1.son1.flag(flag) mother1.flag(flag) There is no compile error. But it doesn´t wrong.. The error is like below: Error: (E112) get interface failed: port is not bound: port 'Top_1.intController1.int0.port_0' (sc_out) In file: c:\data\systemc-2.3.0\src\sysc\communication\sc_port.cpp:230 You said it´s possible to bind cross hierachy, but how it´s realised Thanks
  10. Hey everyone. I´m a newbie in this area. Recently I´m trying to do something with systemC, TLM and OVP..What I´m doing is to 1. model the adc, gpio, memory, uart..(peripherals of ARM-Cortex-M3) with systemC 2. let the adc do some simple tasks and gather the simulation time for a specific step. I guess sc_time_stamp() is a good stuff for gathering the starting and endling time.. 3. give the simulation time the specific current consumption of each peripherals and the cortex.. What´s confusing for me is that 1. when I should put the start time label, and end time label. since there is b_transport between the peripherals and cortex m3. 2. I´m using efm32TG-stk3300. it´s datasheet (http://cdn.energymicro.com/dl/devices/pdf/d0011_efm32tg840_datasheet.pdf, page 26) gives me some details about how the adc on the board works. there are input current, average active current, current consumption of internal voltage reference. Just not sure, which one is for what state. Or there are any two states, idel(input current, current consumption of internal voltage reference), and active (input current, average active current, current consumption of internal voltage reference)? I hope I have made my question clearly thanks in advance
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