In SystemVerilog we can have dynamic unpacked arrays and they can be passed to a function/task. I was wondering if there is a way to pass dynamic packed arrays to a function/task. For example consider the following code:
module test;
logic [3:0] A;
logic [7:0] B;
task automatic double(ref [3:0] val);
val = val * 2;
$display("%b",val);
endtask
initial begin
A = 3;
double(A);
B = 5;
//double(; ** Error because of size mismatch
end
endmodule
here the task can only have a 4-bit input argument so if B is passed an error occurs. I am interested to know if there is any way to pass packed arrays of different size to a task/function. In previous example if the arrays were unpacked I could use:
task automatic double(ref val []);
but I have no idea what I should use for packed arrays. In VHDL having variable size input arguments is very easy. For example the same code can be written like this:
use std.textio.all;
entity test is
end entity;
architecture arch of test is
procedure double(val: bit_vector) is
variable temp : bit_vector(val'left downto val'right);
variable l : line;
begin
temp := val sll 1;
write(l,temp);
writeline(output,l);
end procedure;
begin
process
variable A : bit_vector(3 downto 0);
variable B : bit_vector(7 downto 0);
begin
A := "0011";
double(A);
B := "00001111";
double(;
wait;
end process;
end architecture;
I appreciate any idea on this.
Thanks