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Everything posted by amitk3553

  1. Hello all, What is the meaning of timing annotation like we say blocking and non blocking transports support timing annotations?? Regards Cam
  2. Hello, With the following example, I have a method which is sensitive to an event which is notified(immediately) from end_of_elaboration() function. This gives Segmentation fault (core dumped). However if I do func_event.notify(SC_ZERO_TIME); or func_event.notify(1,SC_NS), there is no Segmentation fault #include "systemc.h" class TOP : public sc_module { public: sc_event func_event; SC_HAS_PROCESS(TOP); TOP(sc_module_name name) { SC_METHOD(method_function); sensitive<<func_event; dont_initialize(); } void end_of_elaboration(){ func_event.notify(); } void method_function() { std::cout<<"inside f() before wait"<<std::endl; } }; int sc_main(int argc, char* argv[]) { TOP top("top"); sc_start(); return 0; } Please have a look, thanks in advance.
  3. amitk3553

    static and dynamic processes

    Hello all, What is the difference between static and dynamic processes? Regards Amit
  4. I want to create VCD file at different location than the directory containing executable. Could I pass the intended path of location for VCD file creation into sc_create_vcd_trace_file("/c/users/xyz/abc") Please give your comments. Thanks.
  5. amitk3553

    Program blocks

    What is the meaning of following "module (design) can not call task/function inside a program block. But a program can call task/function inside module (design)" Please explain it!! Thanks
  6. What does mean by bug of glitch. How can we remove it?
  7. In multi ports we can bind no of initiators to single target socket init_1 ---- init_2 ---- ------- target_socket init_3 ---- in tagged sockets what i understood no of interface method calls on sockets with tagged id to indicate through which socket transaction is coming on single target socket Means difference in multiports and tagged sockets is in tagging. Like in tagged sockets we use ids to indicate the socket through which they come then it would be possible in multiports to use multi port index to know that from which socket, transaction had come. Or TAGGED SOCKETS AND MULTIPORTS ARE SAME CONCEPT except multi port index as tag in MULTIPORTS id as tag in tagged sockets Then What is difference in use-cases of both?
  8. What is the purpose of passing time in b_transport method call in below code? trans.set_data_ptr(data_ptr_host_hci_drive); sc_time to(SC_ZERO_TIME); init_socket->b_transport(trans, to); And what is the meaning of underlined portion in constructor line? hci_ll_monitor(sc_module_name nm): sc_module(nm),
  9. Where is the use of the concept of polymorphism in testbench development in UVM. Please tell me some usecases of polymorphism in testbench development.
  10. What are the differences in IP level and SOC level Verification? Which kind of difficulties we face in SOC level Verification as compared to IP level verification?
  11. amitk3553

    role of dynamic processes

    Why we use dynamic processes, exact role of dynamic processes? In place of these could we use simply static processes?
  12. What is the purpose to make virtual platforms? It just mimics the functionality of hardware?In case if we have hardware,then what is the purpose of virtual plate forms? What are things we explore in architectural exploration?How we do that?
  13. In I2c u would be having suppose 4 clocks. You would implement four clocks in systemC initially using sc_clock construct, then u have to do anding of four clocks to generate single synchronised clock.
  14. amitk3553

    SystemC connect to SystemVerilog Interface?

    Hello sam, May be its possible through UVM connect. i donot know much about it, but if u explore it, u can find some solution. Regards cam
  15. amitk3553

    virtual platforms, architectural exploration

    thanks karandeep, Could somebody throw light on daisy chain equation? Regards cam
  16. Is there some use of TLM 2.0 concepts in UVM?
  17. There are two terms that are added in TLM1.0 to make it TLM2.0? 1) Sockets 2) generic payload Is there are more terms to differentiate TLM 1.0 and TLM 2.0.?
  18. amitk3553

    transaction concept in UVM

    ok, do u know about anything in UVM model of any IP, which we can use in modeling of that IP in systemC. Something common in systemC model and model in UVM for same IP?
  19. amitk3553

    TLM 1.0 and TLM 2.0

    In section 10.1, there are differences Regarding to 1) TLM generic payload 2) Timing annotation 3) const and non const reference One thing, what is about (ports, exports) and sockets. concept of sockets is related to TLM or its in systemC?
  20. What is the difference between configuration object and configuration space in UVM?
  21. I had developed some model(Predictor) in System Verilog in UVM testbench. So Could i use something from existing model into development of SystemC model?
  22. I had seen these terms in UVM methodology.
  23. Please brief the differences b/w ovm and uvm or the modifications done in ovm to develop uvm.
  24. What is constraint solver in SV? What is the meaning of statement if we say that "SV is having powerful constraint solver"?
  25. amitk3553

    Program blocks

    Thanks, One more doubt about "module (design) can not call task/function inside a program block. But a program can call task/function inside module (design)" It means we cannot make instance of module in program block and can make instance of Program block in Module?