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Ahmed

Members
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    4
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About Ahmed

  • Rank
    Member
  • Birthday 01/05/1990

Profile Information

  • Gender
    Male
  • Location
    Kings Langley, UK
  • Interests
    SystemC
    TLM2.0
    System Verilog
    UVM
  1. Ahmed

    Multi port sockets

    Hi Meenakshi, I have no idea about multiple ports, initially I thought TLM is point to point protocol. Imerging from this concept my approach would be introducing a channel (sc_channel) in the middle to regulate transactions, then the targets will be connected to this channel by generating a port per target. there will be one b_transport in the channel to tackel initiator request and triggering multiple processes at the same time, each of them will be dealing with single port (i.e. calling single b_transport in each target). I hope that helps. Thanks, Ahmed
  2. Did you try nchelp. In your case try the command: nchelp ncsc (Error code) if you have an error code for this.
  3. Hi every one, I am testing a bus fabric where several components are connected. I am replacing those components by Systemc models to reduce the simulation time. The bus fabric is the only rtl component. where the TB is in vhdl. The TB instantiate the Systemc components. I wonder if I want to connect a systemc component "instantiated by the TB" to another sysc component "buried inside other component instantiated by the TB" How can I do that using TLM without affecting the instantiator interface. Thanks, Ahmed
  4. Hi every one, I am testing a bus fabric where several components are connected. I am replacing those components by Systemc models to reduce the simulation time. The bus fabric is the only rtl component. where the TB is in vhdl. The TB instantiate the Systemc components. I wonder if I want to connect a systemc component "instantiated by the TB" to another sysc component "buried inside other component instantiated by the TB" How can I do that using TLM without affecting the instantiator interface. Thanks, Ahmed
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