If you require to be unaware of the width of your vector, you can use this:
Yes, its quite a verbose (and ugly) syntax, but on the other hand, VHDL is quite verbose (and ugly ) as well...
Regarding SV lacking this feature - well, it does make sense to me, at least when considering simulators performance (static vs. dynamic arrays, optimization, etc...)
On the other hand, the language does enable you to use dynamic arrays. Moreover, you may quite easily convert them to packed vectors with the streaming operator.