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zcahana

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    zcahana got a reaction from farhad01 in How to pass variable sized packed arguments to a task/function?   
    If you require to be unaware of the width of your vector, you can use this:
    doubler #($bits(A))::double(A);  
    Yes, its quite a verbose (and ugly) syntax, but on the other hand, VHDL is quite verbose (and ugly  ) as well...
     
    Regarding SV lacking this feature - well, it does make sense to me, at least when considering simulators performance (static vs. dynamic arrays, optimization, etc...)
    On the other hand, the language does enable you to use dynamic arrays. Moreover, you may quite easily convert them to packed vectors with the streaming operator.
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    zcahana got a reaction from farhad01 in How to pass variable sized packed arguments to a task/function?   
    Well, there are no dynamic packed arrays in System Verilog.
     
    If the logic of your function is independent of the width of the data, as in your example, then you can use a parameterized class that supply you with the required function.
     
    For example:
     
     
    class doubler #(int unsigned WIDTH = 1); static task double(ref [WIDTH-1:0] val); val = val * 2; $display("%b",val); endtask endclass module test; logic [3:0] A; logic [7:0] B; initial begin A = 3; doubler #(4)::double(A); B = 5; doubler #(8)::double(; end endmodule
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