hbeck

The same way you are doing it without UVM. I'm using a SV wrapper around the VHDL DUT for interface connection. This wrapper will be used in the testbench toplevel. Also the wrapper is perfectly suited to place all cross module references needed by the testbench. vhdlan -work work vhdl_dut.vhd vlogan -v2k -sverilog sv_wrapper_dut.sv vcs -debug_pp -R my_sv_toplevel

Alan is right. You are trying to compile the text file. This example works great for VCS with your given input: module tb; logic [15:0] mem [0:5]; initial begin $readmemb("mem.dat", mem); foreach(mem[i]) $display("mem[%0d]= b%b = d%d", i, mem[i], mem[i]); end endmodule vlogan +v2k -sverilog tb.sv vcs -R tb mem[0]= b1000000000011010 = d32794 mem[1]= b0000000000011010 = d 26 mem[2]= b1000000000011010 = d32794 mem[3]= b1000000000011010 = d32794 mem[4]= b1000000000011010 = d32794 mem[5]= b0000000000011010 = d 26

Hi, I'm pretty new in the world of UVM and need a hint for my first testbench architecture. Thats what I have at the moment: 1. C++ Model that generates Stimuli data + DPI-Interface (SV) 2. DUT (VHDL) 3. C++ Model that generates Compare data for DUT output + DPI-Interface (SV) At first I want to realize only the way of stimuli generation and processing to the DUT. The stimuli generator creates multiple data sets (about 50k bytes each) that need to be feed into the DUT in 32bit partitions. My first Idea was to set up a Consumer/Producer as shown here: C++ / DPI =byte=> Producer =byte=> TLM Fifo =byte=> Consumer =32bit=> Interface =32bit=> DUT Somehow its pretty hard for my as a beginner to map this setup to the general UVM structure (sequence item, sequence, sequencer, driver, ...). Is my producer a sequencer or just producing sequence items? Does my TLM fifo contain sequence items? Is my consumer a driver? (in this case my fifo should hold sequences) Or are all these questions nonsense? Thanks for any help!