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sega

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  1. Hi, set_inst_override_by_type configure factory to create an object of override type when request made to create an object for original type using context that matches the full_inst_path string argument. set_type_override_by_type configure factory to create an object of override type when request made to create an object for original type. Thanks
  2. I am reading a register with using uvm_reg method read_reg. so while doing this read transaction is happening on to the actual bus through agent ,but the I am not getting read value in read_reg task in to a register sequence. so I want to know what could be the issue for not getting read value on to the read_reg task. Regards sega
  3. Hi swapnilm, sorry for delayed reply. Can you once try the same thing with using UVM_NOPACK for each and every field in to packet class, which are present into object utilities. I am not much sure but it showing some packing and unpacking related issue so i think we can try without using internal packing and unpacking utils once. Regards sega
  4. Hi swapnilm, you can do a check between sent packets and monitored packets as below. monitor and driver should connected to same interface and that both components should have a analysis export port ,so whenever your packet is ready to send for comparision you can directly pass those packets with write method of analysis port to the scoreboard ,where u have to declare as a import port and compare with the uvm compare task. as per your question you can directly try to connect driver and monitor with analysis export port in to driver and import port in to monitor.I think it should work with out any outside interface because both is extended from the uvm_component base class. Regards
  5. Hi santhosh, can you try with logic instead of wire for sda pin?
  6. hi santhosh, can you please put here your interface code? Regards sagar
  7. Hi sword_hs. I am trying to get it resolved,but currently my front door access is working and I am focusing on that. so once i will get to know to resolve backdoor issue,that i will keep in this thread. mean while if you are finding any ways to come up from this error Please let us know. Thanks
  8. Hi YYn, Did you got any way to make this non blocking scenario to blocking those read and writes for Register? Thanks in advance.
  9. Hi , I am trying to implement register backdoor access with user defined register backdoor by extending uvm_reg_backdoor. class peri_reg_backdoor extends uvm_reg_backdoor virtual task write(uvm_reg_item rw); $root.top.DUT.reg = 8'h41; endtask endclass when i am compile this code it is showing error illegal location for ahierarchical name (in a package). but in examples i am finding that WRITE method is user define and by giving the hierarchy path of register we can directly configure our registers.I want to know what is the overcome for this issue in IUS. Thanks in advance sagar
  10. hi uwes, I checked with lib installation,,there was having some problem,, that got resolve by support team. Now I am able to run.. thanks again for your inputs.
  11. ok thank you ,,I will check through cadence support system.
  12. yes i am on correct path in hello world example and giving the correct path for uvm home. but 1 supprising thing i am finding is,when i have downloaded uvm-1.0 package and gone inside helloworld example and ran make command it went trough with out any trouble. this problem is comming in package 1.1a and 1.1b. I am not sure if it is a tool issue in between versions of uvm 1.0 and 1.1,
  13. version of uvm is uvm-1.1a and i tried for 1.1b also, ius version is 11.10 command is : uvm-1.1a/examples/simple/hello_world$ irun -access rw -uvmhome ../../../ -quiet +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR -incdir . hello_world.sv
  14. I tried with same command by setting correct uvmhome and fresh new lib downloaded from uvmworld.org but still getting below error. ncsim: *E,MSSYSTF (/home/naveenm/Desktop/sagar/uvm/uvm-1.1a/src/deprecated/uvm_type_utils.svh,33|22): User Defined system task or function registered during elaboration and used within the simulation has not been registered during simulation. $uvm_type_name(r,val);
  15. ------------------------------------------------------------------------------------------------------------ I have downloaded uvm-1.1b lib and i am going to example and trying to run make file which is already exists for ius. in example i am facing the same error. and when i tried with giving -loadpli /auto/tools/INCISIV111/tools/uvm-1.1/uvm_lib/additions/sv/lib/64bit/libuvmpli.so::uvm_pli_boot .and i checked that path this file existance is there but still it is giving same error . so not able to make out what actually problem is. irun -access rw -uvmhome $(UVM_HOME) +UVM_VERBOSITY=$(UVM_VERBOSITY) -quiet +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR -loadpli /auto/tools/INCISIV111/tools/uvm-1.1/uvm_lib/additions/sv/lib/64bit/libuvmpli.so::uvm_pli_boot -incdir . hello_world.sv thanks in advance. regards
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