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Zijay

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  1. Hi All, I'm trying to migrate to UVM 1.2 from 1.1d, but I got the compilation error with NCverilog 12.10, `define uvm_message_add_tag(NAME, VALUE, ACTION=(UVM_LOG|UVM_RM_RECORD)) \ ncvlog: *E,EXPRPP (xxx/UVM/uvm-1.2/src/macros/uvm_message_defines.svh,488|55): expecting a right parenthesis to close the formal arguments to a macro [16.3.1(IEEE)]. Looked at systemverilog code in vm_message_defines.svh :488, I'm wondering whether NCverilog could support this syntax with version 12.10 ? Does UVM 1.2 have any restriction or documentation about the simulator version support ? Thanks.
  2. Hi, I'm now building a uvm_mem model and try the frontdoor access with burst_write and burst_read, all works fine. And I tried to test the backdoor access with peek/poke, after searching for some information, it seems to have uvm_reg_backdoor extension set to uvm_mem first, then I need to implement the virtual task/func "write" and "read_func" in child class of uvm_reg_backdoor. I confused that how to implement those two overloaded "write" and "read_func" ? Seems that should directly write to and read from uvm_mem object, but should they still use frontdoor access "read/write" APIs of uvm_mem or the backdoor way (still peek or poke) ? I ever tried the frontdoor access but it then call to "reg2bus" again, and the simulation is hanged in backdoor way. Can anyone give me some hints or examples ? Thanks in advance !
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