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adhingra

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  1. @ shalsays Yes! I registers the class to the factory with parameter. Only mistake was... Class is declared as class bist_env #(type vif=bist_vif) extends uvm_env ; and I was doing `uvm_component_param_utils(bist_env #(bist_vif) ) Now, I though bist_vif is declared as "typedef virtual interface bist_inf". So it would be treated as virtual. But that's actually a type and not parameter name. Now when registering to factory i gave "vif" and all works well.. `uvm_component_param_utils(bist_env #(vif) ) Does UVM ignores this, and treat it as nothing is passed as parameter. Thanks shalsays for pointing me to factory registration.
  2. Is there anything wrong with the usage of type_id::create method? VCS throws error saying LHS and RHS are not compatible. But we have declared class env_bist_wrap3 with interface type l2bist_inf. Am i missing something here?
  3. Below is the error message. We are creating two classes. One with interface bist_inf and another with l2bist_inf. There is no compile error for creation of first class which is explained below. Line in the error message correspond to env_bist_wrap3 = bist_env #(virtual l2bist_inf)::type_id::create("env_bist_wrap3", this); As the class bist_env is declared with type "type vif=bist_vif" and bist_vif is declared as follows typedef virtual bist_inf bist_vif;" So to me it looks like Factory is treating class "bist_env" of type bist_inf. This is because if i replace the typedef and point bist_vif to other interface which is " l2bist_inf". Then i compile error on creation of first class which is associated with bist_inf. ************** Error-[sV-ICA] Illegal class assignment .....cpa_tests.sv, 86 "this.env_bist_wrap3 = uvm_pkg::__vcs_dummy_uvm_component_registry_20_.create("env_bist_wrap3", this, "\000");" Expression 'uvm_pkg::__vcs_dummy_uvm_component_registry_20_.create("env_bist_wrap3", this, "\000")' on rhs is not a class or a compatible class and hence cannot be assigned to a class handle on lhs. Please make sure that the lhs and rhs expressions are compatible.
  4. I am trying to create a class using factory type_id:: create method and pass virtual interface type as parameter. But i am getting compile error with interface type not compatible. But, If i try to create the class using default "new" method. Everything works fine. Then i can assign the virtual interface any handle using dot "." operator. So the question is does factory type_id create method allows creating classes having interface as parameter? I have created two interface and created one env class that can take interface as parameter. In the top while declaring the ENV class. I am defining both instance with respective interface type. Later while creating, I used factory method which gives compile error. If i replace the factory instance with legacy new method. All works fine. Code looks like : //====================================================================== interface bist_inf (...); … endinterface interface l2bist_inf (...); … endinterface typedef virtual bist_inf bist_vif; class bist_env #(type vif=bist_vif) extends uvm_env ; ...... endclass //====================================================================== class basic_test extends uvm_test; typedef virtual bist_inf L1_bist_vif; typedef virtual l2bist_inf L2_bist_vif; bist_env #(virtual bist_inf) env_bist_wrap2; bist_env #(virtual l2bist_inf) env_bist_wrap3; virtual function void build_phase(uvm_phase); super.build_phase(phase); env_bist_wrap2 = bist_env#(virtual bist_inf)::type_id::create("env_bist_wrap2", this); env_bist_wrap3 = bist_env #(virtual l2bist_inf)::type_id::create("env_bist_wrap3", this); endfunction .. endclass
  5. I am not sure if I understand the UVM callbacks correctly. What I intend to do is when Golden reference model FSM is finished, generate a callback by calling do_callback. So that my virtual sequencer can decide when to kill the sequences running on individual sequencers. Also if required same callback can be used to inform Scoreboard to do final comparison or generate reports. I am not sure if we can register multiple component with same callback. So far I have created 1. Created model_callback class extending from uvm_callback having pure virtual functions. Something like Class model_callback extends uvm_callback; 2. Register this in reference model and call function uvm_do_callback where necessary. `uvm_register_cb(model,model_callback); Also somewhere in the model I did `uvm_do_callbacks(model,model_callback, function_name()); 3. Then I create a class that extends from model_callback.. class custom_callback extends model_callback 4. Wrote implementation of function call here in this class. Funtion that was defined as pure virtual function in model_callback class. 5. In the TOP I created the instance of custom_callback and did uvm_callback #(model,model_callback)::add(model,custom_callback_inst); Now when I run the simulation; Model initiate the callback and I see the function is executed in custom_callback class, which is intended. How can I use the same callback inside other components like scoreboard or virtual sequencers. Or How can i make my sequencer or scoreboard make use of this callback? Can i register or add my scoreboard function to be called automatically when model initiate the callback. Thanks in advance!
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