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David Black

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Everything posted by David Black

  1. Yes, of course. An example would be modeling interrupts, which is often done with an sc_signal<bool>.
  2. Why there is no standard interface class in SystemC

    Java / C# interface is precisely what SystemC interface is. Your original question was more about port aggregation. The problem is that Verilog ports are really quite a different concept. To be sure , there are superficial similarities, SystemC is not an HDL. Mind you, it is quite easy to aggregate SystemC ports. Just define an aggregate class derived from sc_port. This would also allow you to crate aggregate methods (I.e. beyond simple bind). Just don’t expect this to be useable in synthesis. Perhaps a savvy EDA vendor will pickup on This if there is sufficient commercial interest, which I doubt.
  3. Memory Allocation In SystemC

    Using new and malloc are supported for the verification side of SystemC. In other words, when you are creating a validation simulation.
  4. SystemC is very well adopted already and has no need to provide free tools. Also, the purpose of Accellera is to develop standards for the EDA and engineering community, not free tools for academia. For this it has done quite well and continues to do an excellent job. Accellera is made up of volunteers from member companies and many of these do not get paid for their participation. In fact, there are very few that are paid staff for Accellera, and most of those are administrative only without the necessary skills to develop such tools. All contributions for Accellera are strictly volunteer and donations. More to the point, member companies develop and sell tools that do exactly what you are asking. So they have zero motivation to give away what they use to create income for themselves. So if you would like to develop such a tool on your own time and donate it, I am certain others would applaud your efforts; however, you should also not be surprized if your donation is rejected because it might hurt existing products of the member companies. If you would like to get a full time job with one of the member companies, do not be surprised to learn they expect you to have knowledge in SystemC to do some of the work you are hired for. Some companies might even send you to get trained. Finally, if you are interested in "free" tools that convert SystemC to Verilog, you might want to checkout Xilinx Corporation's VivadoHLS, which is as close to free as I think you will get for this type of very complex tool. It is restricted to developing code to be used inside Xilinx FPGA's and does a very decent job. You can also talk with other EDA companies about the possibility as a student of your university acquiring low cost versions of other commercial tools for use in graduate classes.
  5. SystemC for Hardware Design

    For synthesizable SystemC, there is a standard, but even so it is VERY vendor/software dependent. So the answers for using SystemC in a synthesizable context depend on which synthesis software you intend to use. Several companies often software for this (including, but no limited to, Cadence, Xilinx, Mentor (now Siemens)). In general, my experience is that most C/C++ is synthesizable subject to some simple restrictions (e.g. may not use the heap (i.e. new/delete/malloc/free), which also often means you will not be able to use very much of the STL, which is heavily dynamic. Polymorphism is restricted if not forbidden by most of the tools as well. That said, I have successfully synthesized huge designs fairly easily and with decent results.
  6. Simple Bus

    Simple Bus is just a couple of custom channels with fairly simple API. Decode occurs in the bus fabric after interrogating the slaves about their individual address maps. Execution of transfers takes place in the context of respective master threads (initiators). The only other process used is an arbiter. We teach this bus in Fundamentals of SystemC course, which you can learn about here <https://www.doulos.com/content/training/SysC_training.php>. Of course, most folks just skip Simple Bus and go for an implementation based on TLM 2.0. For a Simple Bus application, Loosely Timed would be the appropriate abstraction.
  7. Passing Arguments in the process in SystemC

    Before you go passing arguments to processes in SystemC, I would ask you to be careful of the lifetimes of your variables if passed by reference. Also consider that you could also pass values as class (module) member data.
  8. In general, SystemC models should avoid using clocks altogether. This is good for many reasons assuming your goal is high speed behavioral models. SystemC is often used for implementing functionally accurate virtual platforms that allow software to be designed well ahead of hardware delivery. Thus appropriate use of next_trigger() is actually a great idea. There is no way to distinguish between static and dynamic triggering at the point of invocation. Clock is synthesizable and if that particular mode of design is your goal, then sc_clock is appropriate. There are no features of SystemC itself that will tell you if the code itself is synthesizable. The answer to that is highly tool dependent. I know synthesis tools that require no clock at all, and others that insist a clock be specified. Always keep in mind: SystemC is simply C++ syntax used with a library and a methodology to model hardware and software. C++ has no concept of synthesizability. You have to go beyond GCC/LLVM to find out if your code is synthesizable with a given synthesis tool.
  9. What is the efficiency of SC_THREAD?

    This question cannot be answered with respect to the SystemC standard as the issue is heavily implementation dependent. I am aware of implementations where SC_THREAD is faster than SC_METHOD and visa versa. It is also not a good basis for evaluating SystemC itself since the issue of simulation performance almost always comes down to how SystemC was used and how the modeler wrote their SystemC model. I do know an awful lot of folks use SystemC inappropriately (e.g. using it for modeling RTL, where VHDL or SystemVerilog are much better suited). IEEE 1666-2011 calls out the desired behavior, and not the implementation. Note: I did a presentation on SystemC myths many years ago at NASCUG that included the myth about whether or not one should favor SC_METHOD over SC_THREAD for performance reasons. It is quite simply a poor way of making a decision when attempting to obtain performance.
  10. redefinition of enum

    Study C++ (not C). If you learn C for this, you will get most things wrong and it will be much harder for you. C++ is not a small upgrade to C.
  11. using simple bus

    This is very basic SystemC. Assuming you will use an SC_THREAD, simply do a blocking read from the fifo and write to the appropriate address of the simple bus slave (peripheral). Suggest you take a class on SystemC or spend a lot of time reading up.
  12. redefinition of enum

    I concur with the idea of becoming more proficient in C++. This is the number one best way to improve your SystemC skills. It also helps to get good formal training on SystemC. Suggestions: Define your enum's inside your class declarations (e.g. inside a module). Then you enumeration items become CLASS_NAME::ENUM_NAME Adopt C++11 and use enum classes. See http://en.cppreference.com/w/cpp/language/enum for more details. Do both! Any serious C++ programmer should be using C++11 or C++14 by now unless restricted by some antiquated toolset. These are now well supported by modern versions of GCC, CLANG (LLVM), Microsoft Visual Studio, Oracle, and IBM. This even includes most embedded compilers.
  13. Reading a binary File

    I concur with Maehne's recommendations. Good SystemC requires mastering C++. If you can take a good class, it will accelerate your learning even more. Also, good C++ means throwing out much of your C habits and taking proper advantage of the easier (and safer) to code C++ STL containers and methods.
  14. BlockDiagram to be Converted to SystemC Modules

    Are you doing this for your employer? Perhaps you need to look into getting formal SystemC training. I note that you did not answer the foundational questions I asked in my first response. Waiting...
  15. How exactly sc_main works !!

    Just to add a bit to Philipp's excellent reply: In part this was done to support EDA tools that support co-simulation of SystemC with other languages (e.g. SystemVerilog and VHDL). The EDA tools themselves implement main and then they can dynamically link in your sc_main as needed. Of course if you really know how to control the linker, there are other means as well, but we don't need to go there.
  16. BlockDiagram to be Converted to SystemC Modules

    Is this homework? What are you trying to model? What level are you trying to model? What questions is your model supposed to answer? Until we know what you hope to gain, we cannot reply with anything very useful.
  17. wait() is not suspending the thread

    What does your constructor look like?
  18. help to understand

    That's what the schematic says. No idea what your SystemC code looks like. Also, why would you use SystemC for RTL design? Use SystemVerilog or VHDL instead. SystemC is not suited well to RTL.
  19. cannot understand error

    Pretty much impossible to know exactly what the problem is without the rest of the context. How and were are XMT_datareg and databus defined?
  20. Scope of SC_HAS_PROCESS

    Personally, I prefer to put SC_HAS_PROCESS directly into the constructor body, which works very reliably. All that SC_HAS_PROCESS does is to create a typedef called SC_CURRENT_USER_MODULE which refers to .... the current module name. It is only used in the three macros SC_THREAD, SC_METHOD and SC_CTHREAD. Syntactically, C++ allows a typedef to be created within a function (in this case the constructor function). Advantages of this approach: It's defined very close to the point of usage. The user of a header file, does not need to see it. /.h #import <systemc> // I never use systemc.h ... class Blah: sc_module { Blah(sc_module_name); ~Blah(); } //.cpp file #include "Blah.h" using namespace sc_core; Blah::Blah(sc_module_name nm): sc_module(nm) { SC_HAS_PROCESS(Blah); SC_THREAD(blah_thread); ... } Blah::~Blah(){ }
  21. clock problem

    Seems like a lot more code than needed. Where's the specification? Why are you using sc_int<8> everywhere instead of std::uint8_t ? HINT: sc_int<W> slows down performance and is not needed for 8, 16, 32 or 64 bit types Passing time through the constructor is fine.
  22. Read IEEE 1666-2011 sections 9 & 10. Available for free download from http://www.accellera.org/downloads/ieee. Or watch a free video from https://www.doulos.com/knowhow/systemc/. Or take a class on SystemC & TLM from https://www.doulos.com/content/training/systemc_training.php. TLM 2.0 is a marketable skill and I get many requests for job references. You will need to become proficient at C++, SystemC fundamentals, and then TLM 2.0 in addition to having a good basic knowledge of hardware and software design.
  23. approximately timed

    IEEE 1666-2011 section 10.2 states: IEEE 1666-2011 section 10.3.4 states:
  24. SC_CTOR initialization error ???

    Assumes you are using a version of c++ that supports c++11, just add -std=c++11 to fix this problem or move the constructor arguments to the initializer list of your constructor, which will require abandoning the SC_CTOR macro in favor of full C++ constructor syntax. Or you use the deferred vector construction. Gcc 4.8 or newer supports c++11 if I recall correctly.
  25. All SC_METHOD() not running parallely

    I doubt the reset.neg() is the issue in this case. Furthermore, I disagree that the approach is wrong. Being sensitive to both edges can have a purpose depending on the design. For instance, assuming a positive edge going reset, you might wish to clear various things out on the leading edge and check that they remained so at the trailing edge. The real problem lies somewhere in the methods I strongly suspect. Perhaps the stimuli. We need to see the implementations.