Martin Barnasconi

  • Content count

  • Joined

  • Last visited

About Martin Barnasconi

  • Rank
    Advanced Member

Profile Information

  • Gender
  • Location
    Eindhoven, The Netherlands
  1. UVM-SystemC simulation will automatically finish if all UVM phases have been executed (without any pending objections). You can look in the examples/simple/objections/basic example how to get the objection count. I expect somewhere you raise an objection, but you do not drop it. The SystemC sc_stop will trigger end_of_simulation. So this is expected behaviour. However, in UVM-SystemC you should not call sc_stop yourself (in a similar way, as a user you do not start the simulation with sc_start)
  2. The xutility and the _Adopt method you mentioned are not from the SystemC-AMS library. Who is calling this function? Perhaps you can send a backtrace.
  3. Some remarks/questions: Please try the latest 2.1 version, which can be found here: Can you supply some additional information on the compiler you use on windows: is this gcc in mingw/cygwin or using the msvc compiler. Please supply version Did you try starting the execution using gdb? Is your design using TDF modules only or also LSF and/or ELN?
  4. This could be caused by the famous CRLF incompatibility between Windows/Dos and Unix/Linux. Please try to run dos2unix for all files in the entire systemc tree, and then try again.
  5. This is not a UVM-SystemC library but Eclipse configuration issue. Some things you could check: In the Project Explorer view, the project should be labeled as C/C++ project and contain a subdirectory "Includes". In this list you should see the cygwin and uvm-systemc include directories. If this is not the case, then your project properties are not well defined. Do a Index >> Rebuild Just build the example and see if the error disappear (such build also does start a reindexing Also note that UVM-SystemC puts all classes in the uvm namespace. This means you should explicitly prefix with uvm:: or define a using namespace uvm (only inside method implementations, not in global scope of header files)
  6. There are some commercial and proprietary functional coverage approaches in C++/SystemC, but these are not contributed for standardization. Therefore the WG will work on a new and open standard proposal, along the lines of the initial ideas as presented at NASCUG at DAC2014 (slide 30, 31): Of course this is subject to change. For example, the prefixes will change, as well as some methods and arguments, since we aim for integration in UVM-SystemC.
  7. I expect your SystemC module, as leave cell, uses regular ports (sc_in/sc_out). The SystemC AMS TDF module should use the converter ports (sca_tdf::sca_de::sca_in, sca_tdf::sca_de::sca_out), so it can be connected to regular SystemC modules. This means that the top-level module, which instantiates this SystemC module and the SystemC AMS TDF module, should then a sc_signal, since the input for the SystemC AMS TDF module needs to see this type of signals.
  8. The SystemC AMS 2.1 proof-of-concept in indeed licensed under Apache License, Version 2.0, January 2004. Distribution need to comply to the rules as defined in this Apache 2.0 license. Your package website indeed mentions under license "custom:SystemC-AMS Open Source License". Instead it should state "Apache License Version 2.0, January 2004". My advice is to also contact the developer/maintainer of the PoC, which is COSEDA Technologies GmbH, to inform them on this initiative and to confirm your packaging initiative is recognized/supported:
  9. In your State-space function you did not explicitly specify the time step. In such case, the State-space function will take the module time step. It could be that this module time step is too coarse for your analog State-space equation. In that case, you should specify a more fine-grained timestep as argument for the State-space function.
  10. This is work-in-progress in the Accellera SystemC Verification Working Group. Too difficult to give any estimations on availability, but I suggest to watch for the announcements around Accellera's DVCon events planned later this year. Accellera member companies are encouraged to join the working groups to help in the creation, testing and debug of these important functionalities.
  11. Could you please check with SystemC AMS 2.1 PoC and report if the warning is still there?
  12. The SystemC class library itself does not support this configuration functionality. The UVM-SystemC class library obviously adds this functionality, since we target exactly the same functionality and features as UVM-SystemVerilog.
  13. Please further explain your question: A system-level in SystemC model is often at a higher abstraction than RTL. Do you mean a UVM-SV or UVM-SystemC testbench? Please have a look if your answer is in this FAQ
  14. I expect you have a loop (feedback path) in your design topology. This results in a circular dependency which cannot be resolved by the scheduler. To resolve this, add one time step delay, for example by specifying this delay in one of the output ports in the feedback path.
  15. Can you give some more background on the HLS you are aiming for? Is this HLS for digital or analog functions? For analog HLS (often called analog sizing), I suggest you to contact Laboratoire d’Informatique de Paris 6 (LIP6) at Université Pierre et Marie Curie (UPMC) in Paris, France. More info: