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paragsathe

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Everything posted by paragsathe

  1. Hi, I have a interface monitor where i am capturing data from the interface. I need to pass valid data captured from the interface to the scoreboard for comparison. But the behaviour of interface signals and the way they are asserted depends on the register configuration. Now this config info is not known to the interface or the interface monitor. So while implementing the monitor, should i define two monitors 1) interface monitor which just samples all the data from the bus. 2) process data got in 1) furthur depending on the register config & then pass it on the scoreboard for comparison. Also should this be done using analysis ports? I think this is the right way but wanted to know if there is anything that UVM recommends in such cases. Thanks in advance. Parag
  2. Hi, I want to use a value which is a constant in my VHDL design file. I want to make my env. generic depending on the value of this constant. How do i import this constant from VHDL to SV Thanks, Parag
  3. Methodology wise, is it permissible to use an instance of virtual interface in a virtual sequence for peeking into status signals or enable signals to take the data transfer forward?
  4. But suppose i need the status of a particluar signal to cal a sequence inside a virtual sequencer, is there a way other than peek/poke the interface signals.
  5. Is there any specific reason locking should not be done in the Register model itself and done externally by the user?
  6. paragsathe

    Register model coverage

    Even i am facing an issue with proper sampling of coverage. I have done all the three things above. 1) Covergroups for each register containing individual coverpoints for each field are present in the model generated by using iregGen 2) I am including uvm_reg::include_coverage("*", UVM_CVR_ALL) in the build_phase of my testcase. 3) I am including void'(<addr_block_instance).set_coverage(UVM_CVR_ALL)) in my body of virtual sequence. Still i am not getting proper coverage. I am getting correct hits for some of the register read writes while rest are sampled wrongly. I think the sampling is not happening properly. I am wondering how to debug this?
  7. If we have the register adapter and the regisetr model in place, we generally use the built in read and write methods to access registers in our testbench.But if there is a field related to random number of wait states in the sequence item (transaction item), how to change this parameter while giving the reads and writes to the Bus via the Register model. There is no such field in the uvm_reg_bus_op struct. Parag
  8. I had a quick question. Shouldnt a comparator mismatch be fired as a error by default?
  9. Hi, I am using the built in uvm comparators in my scoreboard. But whenever there is a comparator mismatch, i am getting a warning. What should be done to change this to error? I searched and found that the Comparator mismatch warning is from Line 165 in uvm_in_order_comparator.svh uvm_report_warning("Comparator Mismatch", s); I tried using set_report_severity_id_override, but it didnt work. Thanks. Parag
  10. Sorry Dave, I wasnt specifying the hierarchy. I thought the Message ID is sufficient to find for the component. After specifying the hierarchy, its working now. Thanks you very much for the quick reply Parag
  11. Hi, I am having an issue with Regsiter access layer. I am doing the following in my register read write sequence. 1) Declaring a handle to Register model reg_model_type handle_rm; 2) Declaring a uvm_reg dynamic array and a couple of data items uvm_reg temp_access_regs[$]; rand uvm_reg_data_t data; uvm_reg_data_t ref_data; 3) In body task, i am assigning reg. model to the dynamic array like this handle_rm.get_registers(temp_access_regs); 4) Furthur in the sequence, i am writing values to register bank, shuffling registers, reading back the written values and asserting uvm_error if the values dont match. foreach(temp_access_regs[k]) temp_access_regs[k].write(status,data,.parent(this)); temp_access_regs.shuffle(); foreach(temp_access_regs[j]) begin ref_data = temp_access_regs[j].get(); temp_access_regs[j].read(status,data,.parent(this)); end But the problem i am getting is the get() is returning wrong value. After debugging i found that the mirror values are getting modified with some other register values without me actually writing to them. So the checks are failing. I double checked that i am not doing set or write anywhere else. Why is this happenning? Can anybody help me to solve this issue Thanks. Parag
  12. Hi, I downloaded the vimrc file for UVM. But the problem with it is when i open split windows in a single window, sybtax highlighting does not work for the newly opened files. How can i overcome this problem? Thanks. Parag
  13. If we are using a register layer in our UVM testbench, how to contrain the individual register fields from the testcase? Do we just do it using an object of the register model we have written? can anyone throw some light on this?
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