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timcaputo

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About timcaputo

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  1. Because the uvm_mem implementation breaks burst_write and burst_read transactions into a series of individual transaction and we are using an AXI bus where I want actual bursts, I choose to implement an uvm_reg_frontdoor that could create transactions (1 to max) to be sent to our AXI agent. This worked well until I attempted to have 2 threads simultaneously use that memory to write the design. What I get is the following error: UVM_FATAL @ 705.00 ns: uvm_test_top.va_env.axi2.master_env.master.sequencer@@fd_access_1 [sEQ_NOT_DONE] Sequence uvm_test_top.va_env.axi2.master_env.master.sequencer.fd_access_1 already started What I believe is happening is that for each mem/map there is only a single *instance* of the frontdoor (actually a sequence). The uvm_mem starts this sequence every time it gets a new write or read. For the simultaneous case, this results in the second transaction trying to (re)start the running sequence. This doesn't happen when using a non-user defined frontdoor access because a new sequence_item is created for portion of the burst. If there are are bursts from multiple threads, the start_item() is called on different instances and this allows the agent sequencer to arbitrate. Am I missing something? Is there a better way to get uvm_mem to generate bursts?
  2. I think [/url]http://www.eda.org/svdb/view.php?id=4046 gives some of the information I was talking about. Specifically:
  3. meenu, We are also using the cadence UVC for AXI. I made a reg2_axi_adapter just like the apb example in the user guide by replacing apb_rw with vr_axi::vr_axi_master_burst. There are however, 2 issues with the burst_reads and burst_writes: 1. There is a bug with burst reads where the value needs to be changed to an inout (there are examples in the forum). 2. The uvm_reg_map::do_bus_write and uvm_reg_map::do_bus_read breaks bursts into single transfers. While there may be a better way, I added a frontdoor to the map I using so I could bypass the map's do_write and do_read.
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