Given a class that defines a field:
bit [31:0] foo ;and with said field added to field automation:
`uvm_field_sarray_int(foo, UVM_ALL_ON)I proceed to add a call to my component's build_phase to obtain the results of any configuration changes:
void'(uvm_config_db#(bit[31:0])::get(this, $psprintf("foo[%0d]",i), foo[i]));Doesn't compile.I try:
void'(uvm_config_db#(bit[31:0])::get(this, "foo"), foo));Doesn't compile. It try various other possible permutations. Eventually, I arrive using typedef to avoid syntax limitations in the parameterization clause:
typedef bit[31:0] DW;
typedef DW[0:3] DW_ARRAY;(NOTE: Had to use the [0:3] dimensioning ala Verilog rather than the  dimensioning allowed in SV.)I am now able to deal with uvm_config_db, so long as I deal in terms of the entire array:
void'(uvm_config_db#(DW_ARRAY)::get(this, "", "foo", foo));
This is tolerable, if not ideal, for dealing with static arrays. It does require that configuration overrides deal with the array on an all or nothing basis, but does not permit of modifying a single entry within the array by means of uvm_config_db, so far as I can gather.
So, to the questions:
1) Am I missing something in the syntax? Is it REALLY necessary to do this typedef stuff to con UVM into accepting my data type? If so, couldn't this have been documented up front?
2) Is there any means by which uvm_config_db can be used to modify only a subset of array elements, rather than overriding the entire array?
3) What if some lower-level entity is intended to modify other entries in this array?
4) What about dynamic arrays? In particular, if I have an associative array and wish to override some few specific locations, am I still going to be required to create a separate dynamic array, set my values there, and then pass it in?