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  1. Hi uwes thanks for the response. uvm_hdl_deposit did work. But i had to give the HDL interface instance path. When i tried to use the path of the interface handle in the driver module, the API cound't find the path and gave UVM_ERROR: set: unable to locate hdl path. if possible I dont want to use hard coded hdl path in my verification env. Any reason why uvm_hdl_deposit is not able to work with UVM path?
  2. Hi all Is there a way to use the value of string variable in systemverilog. I have a text file with the pin name and the value to be driven to that pin, on each line. There are around 50 pins. The name of the pin declared in the interface and the text file are same. I want to read the pin name and value from text file into a string and integer. Then use the string to refer the signal in interface and drive the value to it. The code i want to use is roughly as show below. The interface vif has pins pinabc and pinbcd declared in it. obviously here when i use vif.pin the tool is searching for a pin with name "pin" in interface. Is there a way to get the value of the string pin. ----------------file.txt------------------------- pinabc 20 pinbcd 30 ---------------sv code---------------------------------- interger FILE,pin_val; string line,pin; FILE = $fopen("./file.txt","r"); while ($fgets(line,FILE)) begin void'($sscanf(line,"%s %d\n",pin,pin_val)); vif.pin = pin_val; end