jao16

Hello I want to get some feedback regarding any suitable books for UVM. I am looking for tutorial/guidlines/good practices for building UVM test benches. One book i have seen mentioned is "A practical guide to adopting the Universal Verification Methodology (UVM)" by S.Rosenberg and K.Meade. One post said that this book is now out of date - wwas based on UVM 1.0 EA. Any comments on this book ? Are there any books that cover UVM 1.1 release THanks JO

Hello i am extending uvm_sequence_item to define new random data items which will be used to drive the stimulii to the dut. An example being class cmif_seq_data_item extends uvm_sequence_item; `uvm_object_utils(cmif_seq_data_item) // Generate the host Read/Write transactions // randomly. rand bit [31:0] host_wdata; rand bit [3:0] host_wmask ; rand bit [18:0] host_addr; rand bit host_adr_val; rand bit host_rd_n_wr; endclass; Now the host_addr and host_wmask items need to be constrained. host_addr is always word aligned, so i have used constraint c2 {host_addr[1:0] == 2'b00;} Now host_wmask can only take on certain values, for example [0,1,3,7,8 ...] etc To constraint it, i have used constraint c1 {host_wmask inside {4'b0000, 4'b0001, 4'b0011, 4'b0111, 4'b1000, 4'b1001, 4'b1011, 4'b1100, 4'b1101, 4'b1110}; } QS: I don't know if the format for constraint c2 is correct or not. I looked in the 1.1 UVM Users guide and could not find the format for the constraint command to specify valid ranges. I also looked in the UVM Class reference manual 1.0 and could not find the format for the constraint command. QS: Apart form the user guide and the class reference manual is there any other guides/reference/books etc which details the syntax of commands like constraint? Thanks in advance JO

Hello Hello all I am defining a test library as such: package my_test_lib_pkg; class my_test_base extends uvm_test; `uvm_component_utils(my_test_base) // declare an instance of the configuration, environment and agent classes my_cfg cfg_0; my_env env_0; my_agent agent_0; // constructor function new(string name = "my_test_base", uvm_component parent_null); super.ew(name, parent); endfunction : new // Now defining the build() phase. // In the build() phase, i would generate the above classes as such: function void build(); cfg_0 = my_cfg::type_id::create("cfg_0", this); env_0 = my_env::type_id::create("env_0", this); agent_0 = my_agent::type_id::create("agent_0", this); endfunction : build However, in some case i have seen the following code to generate the required instances: cfg_0 = new(); env_0 = new(); agent_0 = new(); So my question is a) what is the difference between create() and new() ? when should one use create() instead of new() and vice versa Thanks in advance JO

Hello Mike Thank you very much for the examples you sent. This will help greatly. Best regards JO

Hello I am building a simple UVM Tbench for a VHDL DUT. QS: How to write the System Verilog wrapper for the VHDL DUT to interface to the UVM test bench? Any pointers would be much appreciated. Thanks JO