loki

The eda.org link is dead. Can you post the new one please?

I need all the info (thread originating the transaction, register name and logic value) in one place (the bus driver) or another (the caller). Does UVM give me this? Since the bus driver drives the physical wires, it knows exactly about the Xs and Zs. But does it know the register name and which thread made the call? Can it be told this info so an error report complete with register name and caller info (thread, file and line) can be printed (assuming my vendor did a decent job with %m or some form of stack trace string)? Thanks.

I have had the worst nightmare with VMM handling Xs because the VMM hides Xs by declaring the register data as bit and not as logic. This makes it a royal pain to debug Xs, and the only way out is to assume that all Xs are bad by putting the following code in the xactor: if ($isunknown(tr.data)) begin `vmm_fatal(log,"Register has X: addr=%h data=%h",tr.addr,tr.data); end Is UVM like this or not?

The uvm_pkg.sv file already includes the macros... this leads me to believe both problems have to do with the compiler.

The error: Following verilog source has syntax error : "myBfm.sv", 12 (expanding macro): token is '#' `uvm_component_utils(myBfm) The code: `include "uvm_pkg.sv" import uvm_pkg::uvm_component; class myBfm extends uvm_component; `uvm_component_utils(myBfm) ... First I did not understand, because this looked exactly like the in examples. Then I decided that instead of importing only the symbols each file needed (e.g. import uvm_pkg::uvm_component), I would try to import everything at the top level (i.e. import uvm_pkg::*). Doing so, the error went away, but the compiler simply hangs forever during parsing with not hints as to what is wrong.

Page 215 of the UVM 1.1 Class Reference: class env extends uvm_component; `uvm_component_utils(comp1) Should say "`uvm_component_utils(env)". Has the code been tested? I am trying to learn uvm...

Is the UVM an all-or-nothing type of library? By that I mean is it possible to use only portions of it by selecting which uvm files to include? Are the uvm files individually self-contained (e.g. does each file include the files it needs and so on)? For example, if I just want the reporting macros, do I need to bring in the whole framework?

I have run into this problem as well. Where can the patch be downloaded? In general, is there a form of public access to the source code repository (which I guess contains the commits of all the fixes since the official release)?

The UVM prints a report at the end of the simulation. Is it possible to reorder the end of simulation report it in the following order: - report counts by id (or turn off this one) - report counts by severity - the error or fatal that caused the simulation to end The idea is to print the error or fatal as close as possible to the bottom of the logfile (no scrolling, no grepping). Thanks

Can I get the UVM to end the simulation with a non-zero exit status to the operating system when there is a UVM_ERROR or a UVM_FATAL?

In the UVM user guide (18-May-2011 p. 122), it says to use the following: regmodel.set_auto_predict(1); But this does not compile! It seems the set_auto_predict is a method of the UVM register map: regmodel.APB.set_auto_predict(1); Is this a documentation bug or is the ralgen generated model buggy?

How do end users of the UVM enter bugs or feature requests to the Mantis database? Also, I don't see a UVM project in the Mantis database, how/where are UVM related issues tracked?

On page 5, what is "uvm_reg_reg" in "class reg_slave_ID extends uvm_reg_reg"? Shouldn't it be "uvm_reg"?

The Synopsys ralgen generated code causes this problem... I have to post-process the sv code with sed to fix the problem since the source for ralgen is not open. I agree, it should use uvm_report and not $display(), but I'll let the gurus decide on this one.

I see. To each block of the entire register model corresponds a sub-environment, which gets a pointer to just that block of the register model. Thanks.