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DavidLarson

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  1. DavidLarson

    Validating IPXact

    For 1: You can use the schema files provided by Accellera. Run them with xmllint. For 2: No. Pretty sure there isn't an open-source tool to do that for you.
  2. DavidLarson

    Referencing the memoryMap of a sub-component

    Forget my last question. I believe I figured it out. Now to figure out how to put hdl_paths in a hierarchy....
  3. DavidLarson

    Referencing the memoryMap of a sub-component

    Thank you Erwin. Yes that does help. Our situation is a little different, where we have a hierarchy of components, each with their own bank of registers. So, we won't be looking to connect sibling components, but connections would be from parents to children. Can that be done with IPXACT?
  4. DavidLarson

    Referencing the memoryMap of a sub-component

    Hi Erwin, Thank you for the info. I've been reading through the User Guide and it doesn't seem to provide all the info I need to do this. For example, in section 3.1.6 it says: Yet, it doesn't explain how to put a memoryMap in an addressSpace. You can only put segments in addressSpaces, not memoryMaps. Can you please provide an example of what that would look like? Regards, David
  5. I'm going through the HAL documentation and it looks l like the only languages that HAL supports are: Verilog, VHDL, SystemC and e. No system verilog. Rats.
  6. I have found a related problem. When you need to send a 1 to a W1C register field, the normal flow doesn't work: register_model.register.w1c_field.set(1); // <--- this is set to 0 internally register_model.register.update(status); This is clearly not what the user expects. What is the correct flow for these registers?
  7. I can see that the uvm_heartbeat hasn't been updated to fix this bug: http://forums.accellera.org/topic/1256-bug-uvm-heartbeat-does-not-respect-the-comps-list
  8. DavidLarson

    Welcome to the UVM 1.2 Public Review

    I can see some very old code that should be cleaned up (such as the uvm_in_order_comparator). What is the timeline for a general code clean up?
  9. I just compiled your code (I added the endclass keyword): class addr_hole_seq extends uvm_sequence # (uvm_sequence_item); `uvm_object_utils(addr_hole_seq) endclass and it compiled fine. Now you need to check elsewhere ... the code preceding this, how you are compiling, etc.
  10. I see errors like this when the macro is not called correctly. Check these: If the object is parameterized you should be using `uvm_object_param_utils (<object_name>#(<parameters>)). make sure that the argument to the macro contains the name of the class and there are no typos. Make sure the registration macro isn't called more than once. Other than that, it would be helpful to see your source code.
  11. Hi Jadec, Yes, that makes sense. Thanks, David
  12. Hi Jadec, I agree that the get function is expensive, but calling it from the sequencer (rather than the sequence) is just as expensive since it is called the same number of times either way. David
  13. Hi mrforever, I just checked the UVM 1.1d library and the macro still exists. (phew!) You should email your question to support@synopsys.com (I think that's the right address) and a FAE will get back to you. Good luck! David
  14. If you are using a pre-compiled version of the UVM library then the macro will not change it. If you are not using a pre-compiled UVM library, then I would contact the Synopsys FAE and ask them what needs to change in your compile flow. I'm sure that the fix is something simple.
  15. Yes, I agree Logger. Since you have several items in your TB needing this setting then using the configuration DB is the way to go (vs. setting the items directly). BTW: Have you tried using uvm_resource_db instead?
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