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qwerty

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  1. yes, i am using uvm_reg. There are 3 separate interfaces pcie, spi and i2c which can access same set of registers/memory. Thanks
  2. Hi, We have single register space and 3 masters can accessing that space. I want all the masters to access those registers parallely. What can be the best possible way to do it. Currently, I have to select one at compilation time. Thanks
  3. I want to model a memory of depth 2048 and width 64 bits. Currently I doing as below and when i am running the walk_mem sequence, its going from 0 to 2048 rather than 2047. super.new(name, 'h101, 64, "RW", UVM_NO_COVERAGE) Thanks in advance
  4. Hi, I want to use the "uvm_debug" verbosity but i couldn't find it in uvm1.1/1.2 class reference user guide. Thanks
  5. Hi, I there a limitation to the number of registers that can be handled by uvm register model? if yes, whats the count. QW
  6. Hi, While doing force using "uvm_hdl_force", i am getting the below error and the specified memory location is not written with that value. But it works using "force". Any solution to this. ERROR: VPI NOFORCO vpi_put_value() cannot force object of type: vpiReg. Thanks QW
  7. Hi Uwe, Any specific reason why not to use the uvm_hdl_force directly? -QW
  8. used $sformatf to pass it to a string a pass that string to uvm_hdl_force(). thanks for the solution.
  9. Hi, I my using uvm_hdl_force("path",data) to configure the registers of the design. But the problem is they are large in number so i want to loop them in. for(int i=0; i<8; i++) begin for(int j=0; j<8; j++) begin uvm_hdl_force("DUt.abc.pkt.reg_0.w[1]" , data); end end I want to replace 0 with i and 1 with j . Is their a simple way to do it.
  10. Thanks tudor, that is a nice way to get the access policy of registers if all the fields have same access policy.
  11. Hi, How can i get the access policy of a register? For fields its possible to get using get_access(). Is their a way to extract the "Registers" from the model with RW access policy ? Thanks.
  12. UVM reg model mask

    Thanks guys for the help..
  13. UVM reg model mask

    I have modeled the unused bits as "rsvd" in the model. but the issue is, the dut still writes on those unused bits. So while i do a mirror, it fails as the dut has all 1's (if i write all 1's ) but the model writes according to the mask in it. So how can i disable the check or what access policy to use to disable it. Thanks
  14. Hi, I have a 32 bit register in which some of the bits are reserved. I have added the mask in the register model. But the reserved bits are also read/writable. I only wont to write to the bits which are not reserved. foreach (rg) begin foreach (fields[j]) begin if (fields[j].get_name() == "UNUSED" ) begin $display("UNUSED field= %s",fields[j].get_name()); end else begin fields[j].write(status, wdata,.parent(this)); end end I tried the obove solution, but it writes for every field which is slowing me down. Is their a way i can get the mask from the register model? Or any other solution? Thanks
  15. Hi, I have a sequence running but i want to delay that sequence for 50 clk. How can i do it from the test. Is reset_phase a good option in the test class? or is their another way out. thanks
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