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scnix1

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  1. Mentor has a tool called "Register Assistant" that does this, but I've never used it for RTL and only done limited testing with it for UVM. Scott Nixon
  2. I'm trying to model some internal registers and memories using the UVM Register Package. I am not doing auto prediction; I'm trying to do set() and get() to do the prediction. It works fine for registers, but there is no get() method for the uvm_mem class? Is there a clean way to do a non-time consuming (i.e. function not task) method to directly set and get memory model values? Thanks, Scott Nixon
  3. That did indeed fix it. Flipping through the Cookbook I can not find a direct reference to it, my guess is it was an inadvertent auto-complete via Certe that gave me the code. That's what I get for indiscriminately banging on the tab key. Thanks! Scott Nixon
  4. Trying to use the UVM register package with Questa 10.0a_1 and get the following error: # ** Error: (vsim-3667) Reg2PacketAdapter.sv(13): Automatic task/function item 'create_object' cannot be accessed by hierarchical reference. # Region: /packet_agent_pkg I can get past it by changing the "...type_id::create_object.." call by a simple new() Unable to find anything on this error on the Mentor site expect for a different issue that recommended using -novopt. Tried it both ways, made no difference. My code is pretty much straight out of Mentor's "UVM Methodology Cookbook". Anyone else seen this? Thanks, Scott Nixon
  5. OK, thanks. So what is the currently recommended procedure for raising objections from sequences? Scott Nixon
  6. I see where raising objections via uvm_test_done is deprecated, yet I don't see any other way to effectively raise them from a sequence as it does not have a run_phase() task defined. I tried using starting_phase, but it is null. Apparently this is a known issue: http://www.eda.org/svdb/bug_view_page.php?bug_id=3419&history=1 Thanks, Scott Nixon
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