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Everything posted by dave_59

  1. This was recently discussed here. The assertion should fail because disable_assert is false at the start of the attempt.
  2. dave_59

    Connect interface to dut

    Change the interface signal to a wire.
  3. dave_59

    Using parametrized class in package

    Works for me in Questa, and in the VCS on edaplayground.com. I mean I get no compilation errors, did not check the functionality of your code. Maybe you are using an older version, Also, I suggest using *.SystemVerilog as file extension of using *.v and -sverilog switch. That helps keep legacy Verilog files working.
  4. dave_59

    Significance of type_id

    It is the name of a class typedef added by the `umm_object_utils or `umm_component_utils factory macros and you are using type_it::create() to access a static method in that class. I explain the macro in this blog post. I explain how the UVM implements the factory in more detail in my SystemVerilog OOP for UVM course.
  5. You could extend your class from uvm_report_object. But this also creates a uvm_report_handler object which has a lot of overhead. A few other options are Avoid using a nested class. What is it doing for you in this situation? Define the class bar at the same level as foo. Avoid using the `uvm_field macros - also a lot of overhead.
  6. dave_59

    'starting phase' - intended usage

    You might want to see http://forums.accellera.org/topic/1967-problems-with-starting-phase/
  7. dave_59

    Problems with starting_phase

    New link to mantis issue https://accellera.mantishub.io/view.php?id=4969
  8. dave_59

    UVM Phases: end_of_elobration

    The original intent of the phases in the OVM was to help with the initialization and shutdown of a simulation. The OVM phases mimic what happens in other environments like SystemC. end_of_elaboration is after all the elements of your testbench are constructed, and start_of_simulation is the initialization of your testbench. The phases make good breaking points for debug and checkpoints for restoring. The problem with phases in general is that unless you get everyone to universally agree on what goes in each phase, they lose their effectiveness.
  9. I would use the forum on EDAplayground to contact them,
  10. I think the problem is with EDAplayground.com appending extra characters at the end of each line. Look carefully at the error messages coming from each tool and you'll see a good explanation of the problem. I believe Aldec is incorrectly ignoring that extra character, so it appears that it is "working".
  11. This works for me in Modelsim/Questa. Note that the newline has been escaped and the resulting string will be displayed as a single line. If you want a newline embedded in the string, you need to add \n.
  12. Hi Linc, No to your first query. There is a difference when interacting with clocking block inputs ##0 delays. The clocking block event cb1 is guaranteed to happen after the clocking block inputs have been updated with sampled values,and ##0 will never block. My general rule when you have a process interacting with clocking block inputs and outputs, always synchronize that process to the clocking block event. And yes to your second query, unless a clocking block output is driving an input to the interface.
  13. Use uvm_config_db#(BaseA)::set() to match the uvm_config_db#(BaseA)::get() Then you need to test the result of the $cast to know if the object was overridden or not.
  14. dave_59

    build_phase order

    It's an artifact of the UVM implementation that stores the children (siblings) in an associative array indexed by a string. I would never rely on the ordering of components at the same level within the same phase.
  15. Hi Walker, Communicating time values across multiple timescale domains has been a gotcha in Verilog since day one. Timescales only apply to scaling of literal time values, not values of variables or passed arguments. Therefore, you should always use a literal time value in any expression involving time to a normalized time unit. Unfortunately, they didn't do this inside the UVM library. So if your UVM package is compiled with a default of timescale of 1ps, then you should do this to normalize it : uvm_top.set_timeout(2000000ns/1ps, 1); -Dave
  16. dave_59

    Help regarding fork_join usage

    You use fork/join_any statements when you want to create a number of time consuming processes and block waiting for one of them to finish. You create two processes, but they do not bloc - the finish immediately because they have fork/join_none statements in them . What you probably meant was something like initial begin me[0] = 1; me[1] = 2; me[2] = 3; repeat(5) begin : repeat_loop fork begin : b1 foreach(me) fork automatic int id = me; print_value (10+id,id); join_none wait fork; end : b1 begin :b2 foreach(me) fork automatic int id = me; print_value (20+id,id); join_none wait fork; end : b2 join_any disable fork; $display(" Disable Fork "); end :repeat_loop $display("@%g Came out of fork-join", $time); #20 $finish; end // initial begin
  17. already answered here:https://verificationacademy.com/forums/systemverilog/use-intersection-cross-coverpoints
  18. dave_59

    randomize() with inside syntax

    The syntax is assert ( randomize(index) with { index inside { [1:5] } ; } ) else begin It's the same {} as if you wrote named constraint block. Each constraint within the {} needs to be terminated with a semi-colon constraint range_constraint { index inside { [1:5] } ; }
  19. This question is very vague. C programs don't have the concept of event triggers or delays. But SystemVerilog can use event triggers or delays to schedule when you call a C code from the DPI, and C code can in turn call SV code that has event triggers and delays.
  20. What is not clear is why you expect c.a to be 10. Because of the assignment p.c = c;, c.a and p.c.a are the same random variable.
  21. dave_59

    walk thru an enumeration

    You can use a do-while loop: module top; //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek; //to show default assignments typedef enum {alpha, beta, gamma, delta, epsilon} greek; greek letters; initial begin $display("****** Walk thru an enumeration example. ***********"); letters = letters.first; do begin $display(" %0d *** %0s", letters, letters.name); letters = letters.next; end while (letters != letters.first); end endmodule : top
  22. dave_59

    Output `uvm_info to file

    Use *_hier to set all components below the top level. (I don't know why they abbreviated hierarchy) uvm_top.set_report_default_file_hier(log_file); uvm_top.set_report_severity_action_hier (UVM_INFO, UVM_DISPLAY | UVM_LOG);
  23. dave_59

    Index Pool Mgmt

    I don't think the UVM provides a class for that, but you can easily model that with a simple constraint on any member of a class. class myclass; int pool_of_devices[$]; rand int device; constraint new_device { !( device inside {pool_of_devices} ); } function void post_randomize(); pool_of_devices.push_back(device); endfunction endclass
  24. An interface class is not the same as a plain interface. The interface keyword in front of a class type definition is special modifier, like the virtual keyword that defines a special type of class. The BNF shows you the syntax that is possible to express, but not all of it is necessarily legal. Any syntax that is not expressible is illegal. If you scan through this series of BNF items, you will observe that there is no way to assign an interface/module/program to a type parameter. If you go through the list of data_type items, there is nothing that allows an interface_identifier unless it is preceded by the virtual keyword.