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dave_59 last won the day on August 28

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  1. This was recently discussed here. The assertion should fail because disable_assert is false at the start of the attempt.
  2. dave_59

    Connect interface to dut

    Change the interface signal to a wire.
  3. dave_59

    Using parametrized class in package

    Works for me in Questa, and in the VCS on edaplayground.com. I mean I get no compilation errors, did not check the functionality of your code. Maybe you are using an older version, Also, I suggest using *.SystemVerilog as file extension of using *.v and -sverilog switch. That helps keep legacy Verilog files working.
  4. dave_59

    Significance of type_id

    It is the name of a class typedef added by the `umm_object_utils or `umm_component_utils factory macros and you are using type_it::create() to access a static method in that class. I explain the macro in this blog post. I explain how the UVM implements the factory in more detail in my SystemVerilog OOP for UVM course.
  5. You could extend your class from uvm_report_object. But this also creates a uvm_report_handler object which has a lot of overhead. A few other options are Avoid using a nested class. What is it doing for you in this situation? Define the class bar at the same level as foo. Avoid using the `uvm_field macros - also a lot of overhead.
  6. dave_59

    'starting phase' - intended usage

    You might want to see http://forums.accellera.org/topic/1967-problems-with-starting-phase/
  7. dave_59

    Problems with starting_phase

    New link to mantis issue https://accellera.mantishub.io/view.php?id=4969
  8. dave_59

    UVM Phases: end_of_elobration

    The original intent of the phases in the OVM was to help with the initialization and shutdown of a simulation. The OVM phases mimic what happens in other environments like SystemC. end_of_elaboration is after all the elements of your testbench are constructed, and start_of_simulation is the initialization of your testbench. The phases make good breaking points for debug and checkpoints for restoring. The problem with phases in general is that unless you get everyone to universally agree on what goes in each phase, they lose their effectiveness.
  9. I would use the forum on EDAplayground to contact them,
  10. I think the problem is with EDAplayground.com appending extra characters at the end of each line. Look carefully at the error messages coming from each tool and you'll see a good explanation of the problem. I believe Aldec is incorrectly ignoring that extra character, so it appears that it is "working".
  11. This works for me in Modelsim/Questa. Note that the newline has been escaped and the resulting string will be displayed as a single line. If you want a newline embedded in the string, you need to add \n.
  12. Hi Linc, No to your first query. There is a difference when interacting with clocking block inputs ##0 delays. The clocking block event cb1 is guaranteed to happen after the clocking block inputs have been updated with sampled values,and ##0 will never block. My general rule when you have a process interacting with clocking block inputs and outputs, always synchronize that process to the clocking block event. And yes to your second query, unless a clocking block output is driving an input to the interface.
  13. Use uvm_config_db#(BaseA)::set() to match the uvm_config_db#(BaseA)::get() Then you need to test the result of the $cast to know if the object was overridden or not.
  14. dave_59

    build_phase order

    It's an artifact of the UVM implementation that stores the children (siblings) in an associative array indexed by a string. I would never rely on the ordering of components at the same level within the same phase.