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dave_59

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dave_59 last won the day on August 28 2018

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  1. dave_59

    constraint dist 'others'

    https://verificationacademy.com/forums/systemverilog/distributed-weightage-constraint#reply-46525
  2. You always incur overhead for automation. Performance rapidly deteriorates as you introduce dependencies with other random variables. For example, suppose you need 8 unique values between 10 and 20. You are going be calling $urandom_range many extra times throwing away values that don't meet the constraints. And it becomes very difficult to know when there are no solutions, and you end up in infinite loops looking for solutions that are very hard to find or don't exist. This is what a constraint solver does for you. Since constraints are tied to the class inheritance system, they provide another key benefit: you can add to or override them easily. It's very difficult to override constraints embedded within procedural code (this includes using in-line constraints).
  3. Where did you read 0 is not a valid seed?
  4. Give your error message a unique ID. Use set_report_severity_id_override to change the severity of that ID from UVM_ERROR to UVM_INFO. Then call get_id_count at the end of your test to make sure it's non-zero.
  5. dave_59

    Log File Parsing

    The return code usually indicates successful completion of the tool and is unrelated to completion of the test. Non-zero return codes would be OS specific error codes. The SystemVerilog standard way of indicating pass/fail status is using the $info/$warning/$error/$fatal messages. Most tools are essentially catch the UVM reports and convert them to one of the SystemVerilog messages. They also have a way of detecting the most severe message issued during a run and you can use that information for determining pass/fail status.
  6. This was recently discussed here. The assertion should fail because disable_assert is false at the start of the attempt.
  7. dave_59

    Connect interface to dut

    Change the interface signal to a wire.
  8. dave_59

    Using parametrized class in package

    Works for me in Questa, and in the VCS on edaplayground.com. I mean I get no compilation errors, did not check the functionality of your code. Maybe you are using an older version, Also, I suggest using *.SystemVerilog as file extension of using *.v and -sverilog switch. That helps keep legacy Verilog files working.
  9. dave_59

    Significance of type_id

    It is the name of a class typedef added by the `umm_object_utils or `umm_component_utils factory macros and you are using type_it::create() to access a static method in that class. I explain the macro in this blog post. I explain how the UVM implements the factory in more detail in my SystemVerilog OOP for UVM course.
  10. You could extend your class from uvm_report_object. But this also creates a uvm_report_handler object which has a lot of overhead. A few other options are Avoid using a nested class. What is it doing for you in this situation? Define the class bar at the same level as foo. Avoid using the `uvm_field macros - also a lot of overhead.
  11. dave_59

    'starting phase' - intended usage

    You might want to see http://forums.accellera.org/topic/1967-problems-with-starting-phase/
  12. dave_59

    Problems with starting_phase

    New link to mantis issue https://accellera.mantishub.io/view.php?id=4969
  13. dave_59

    UVM Phases: end_of_elobration

    The original intent of the phases in the OVM was to help with the initialization and shutdown of a simulation. The OVM phases mimic what happens in other environments like SystemC. end_of_elaboration is after all the elements of your testbench are constructed, and start_of_simulation is the initialization of your testbench. The phases make good breaking points for debug and checkpoints for restoring. The problem with phases in general is that unless you get everyone to universally agree on what goes in each phase, they lose their effectiveness.
  14. I would use the forum on EDAplayground to contact them,
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