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  1. Hi Dave, I tried your new Makefile.questa, but QuestaSim 10.2c could not work both on Linux version (32bits mode in Makefile) and on Win7_64 OS with Cygwin64 tool (64bits mode in Makefile / gcc-4.5.0-mingw64). Here are the full error messages. 1. The errors in QuestaSim vlog 10.2c Linux version with 32bits vlib work vlog -timescale "1ns/1ns" ../../../../src/dpi/uvm_dpi.cc -ccflags -DQUESTA -writetoplevels questa.tops +incdir+../../../../src ../../../../src/uvm.sv +incdir+. \ top.sv QuestaSim vlog 10.2c Compiler 2013.07 Jul 18 2013 -- Compiling package uvm_pkg ** Warning: ../../../../src/base/uvm_event.svh(39): (vlog-2181) Use of a parameterized class uvm_event_callback as a type creates a default specialization. -- Compiling package user_pkg -- Importing package uvm_pkg -- Compiling module top -- Importing package user_pkg Top level modules: top -- Compiling DPI C/C++ file ../../../../src/dpi/uvm_dpi.cc vsim -voptargs=+acc=rmb -c -do "run -all; q" -l questa.log -f questa.tops Reading pref.tcl # 10.2c # vsim -do {run -all; q} -l questa.log -voptargs=+acc=rmb -c top # Loading /var/tmp/romwang@cybvgar-nx23_dpi_29739/linux_gcc-4.5.0/export_tramp.so # ** Note: (vsim-3812) Design is being optimized... # ** Warning: ../../../../src/base/uvm_tr_stream.svh(494): (vopt-2250) Function "do_open_recorder" has no return value assignment. # ** Warning: ../../../../src/base/uvm_recorder.svh(678): (vopt-2250) Function "check_handle_kind" has no return value assignment. # ** Warning: ../../../../src/tlm1/uvm_sqr_ifs.svh(248): (vopt-2250) Function "is_auto_item_recording_enabled" has no return value assignment. # // Questa Sim # // Version 10.2c linux Jul 18 2013 # // # // Copyright 1991-2013 Mentor Graphics Corporation # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS # // LICENSORS AND IS SUBJECT TO LICENSE TERMS. # // # Loading sv_std.std # Loading work.uvm_pkg(fast) # Loading work.user_pkg(fast) # ** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled "questa_uvm_pkg" can be found. # This also means that later if you turn on UVM-aware debugging your debug simulations may have # different random seeds from your non-debug simulations. # Loading work.top(fast) # ** Error: (vsim-3978) ../../../../src/base/uvm_transaction.svh(487): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Error: (vsim-3978) ../../../../src/base/uvm_transaction.svh(676): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Error: (vsim-3978) ../../../../src/base/uvm_component.svh(2597): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Error: (vsim-3978) ../../../../src/base/uvm_component.svh(2810): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Error: (vsim-3978) ../../../../src/base/uvm_component.svh(2762): Illegal assignment to class work.uvm_pkg::uvm_event #(class work.uvm_pkg::uvm_object) from unknown class type # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # Error loading design Error loading design make: *** [run] Error 12 2. The errors in QuestaSim vlog 10.2c win64 in Win7_64 OS and Cygwin64 tool (64bits mode in Makefile / gcc-4.5.0-mingw64) [Administrator@PC201408061944 ...sequence/basic_read_write_sequence]$ make -f Makefile.questa all vlib work vlog -timescale "1ns/1ns" -ccflags -DQUESTA -writetoplevels questa.tops +incdir+../../../../src ../../../../src/uvm.sv +incdir+. \ top.sv QuestaSim-64 vlog 10.2c Compiler 2013.07 Jul 19 2013 -- Compiling package uvm_pkg ** Warning: ../../../../src/base/uvm_event.svh(39): (vlog-2181) Use of a parameterized class uvm_event_callback as a type creates a default specialization. -- Compiling package user_pkg -- Importing package uvm_pkg -- Compiling module top -- Importing package user_pkg Top level modules: top vsim -voptargs=+acc=rmb -c -do "run -all; q" -l questa.log -f questa.tops Reading D:/questasim64_10.2c/tcl/vsim/pref.tcl # 10.2c # vsim -do {run -all; q} -l questa.log -voptargs=+acc=rmb -c top # Loading C:\cygwin64\tmp\Administrator@PC201408061944_dpi_4772\win64_gcc-4.5.0\export_tramp.dll # ** Note: (vsim-3812) Design is being optimized... # # ** Warning: ../../../../src/base/uvm_tr_stream.svh(494): (vopt-2250) Function "do_open_recorder" has no return value assignment. # # ** Warning: ../../../../src/base/uvm_recorder.svh(678): (vopt-2250) Function "check_handle_kind" has no return value assignment. # # // Questa Sim-64 # // Version 10.2c Unknown Platform Jul 19 2013 # // # // Copyright 1991-2013 Mentor Graphics Corporation # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS # // LICENSORS AND IS SUBJECT TO LICENSE TERMS. # // # Loading sv_std.std # Loading work.uvm_pkg(fast) # Loading work.user_pkg(fast) # ** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled "questa_uvm_pkg" can be found. # # This also means that later if you turn on UVM-aware debugging your debug simulations may have # # different random seeds from your non-debug simulations. # # Loading work.top(fast) # Compiling C:\cygwin64\tmp\Administrator@PC201408061944_dpi_4772\win64_gcc-4.5.0\exportwrapper.c # Loading C:\cygwin64\tmp\Administrator@PC201408061944_dpi_4772\win64_gcc-4.5.0\dpi_auto_compile.dll # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_hdl_check_path' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_hdl_deposit' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_hdl_force' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_hdl_release_and_read' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_hdl_release' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_hdl_read' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_dpi_get_next_arg_c' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_dpi_get_tool_name_c' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_dpi_get_tool_version_c' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_dpi_regcomp' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_dpi_regexec' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_dpi_regfree' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_re_match' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_dump_re_cache' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # ** Warning: (vsim-3770) Failed to find user specified function 'uvm_glob_to_re' in DPI C/C++ source files. # Time: 0 ns Iteration: 0 Region: /uvm_pkg File: ../../../../src/uvm_pkg.sv # run -all # ** Fatal: (vsim-160) ../../../../src/dpi/uvm_svcmd_dpi.svh(27): Null foreign function pointer encountered when calling 'uvm_dpi_get_next_arg_c' # Time: 0 ns Iteration: 0 Process: /uvm_pkg/#INITIAL#212 File: ../../../../src/dpi/uvm_svcmd_dpi.svh # Fatal error in Module uvm_pkg at ../../../../src/dpi/uvm_svcmd_dpi.svh line 27 # # HDL call sequence: # Stopped at ../../../../src/dpi/uvm_svcmd_dpi.svh 27 Module uvm_pkg # called from ../../../../src/dpi/uvm_svcmd_dpi.svh 32 Module uvm_pkg # called from ../../../../src/base/uvm_cmdline_processor.svh 247 Function uvm_pkg/uvm_cmdline_processor::new # called from ../../../../src/base/uvm_cmdline_processor.svh 62 Function uvm_pkg/uvm_cmdline_processor::get_inst # called from ../../../../src/base/uvm_root.svh 339 Function uvm_pkg/uvm_root::new # called from ../../../../src/base/uvm_root.svh 271 Function uvm_pkg/uvm_root::m_uvm_get_root # called from ../../../../src/base/uvm_coreservice.svh 184 Function uvm_pkg/uvm_default_coreservice_t::get_root # called from ../../../../src/base/uvm_root.svh 326 Function uvm_pkg/uvm_root::get # called from ../../../../src/base/uvm_root.svh 315 Module uvm_pkg # # q Makefile.questa:34: recipe for target 'run' failed make: *** [run] Error 1
  2. Hi Dave, Above question is based on linux version. My friend also tired the Questa Sim-64 10.2c win64 to compile the UVM-1.2 example. but he met following error. do you have any suggestion? [Administrator@PC201408061944 ...sequence/basic_read_write_sequence]$ make -f Makefile.questa all make -f Makefile.questa LIBNAME=uvm_dpi BITS=64 dpi_libWin make[1]: Entering directory '/home/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' mkdir -p ../../../../lib d:/questasim64_10.2c/gcc-4.5.0-mingw64/bin/g++.exe -g -DQUESTA -W -shared -Bsymbolic -Id:/questasim64_10.2c/include -I../../../../src ../../../../src/dpi/uvm_dpi.cc -o ../../../../lib/uvm_dpi.dll d:/questasim64_10.2c/win64/mtipli.dll -Id:/questasim64_10.2c/gcc-4.5.0-mingw64/include -lregex C:\cygwin64\tmp\cc46pq7f.o: In function `m_uvm_report_dpi': C:\cygwin64\home\uvm-1.2\examples\simple\sequence\basic_read_write_sequence/../../../../src/dpi/uvm_common.c:33: undefined reference to `m__uvm_report_dpi' collect2: ld returned 1 exit status ../../../Makefile.questa:167: recipe for target 'dpi_libWin' failed make[1]: *** [dpi_libWin] Error 1 make[1]: Leaving directory '/home/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' ../../../Makefile.questa:174: recipe for target 'dpi_lib64' failed make: *** [dpi_lib64] Error 2
  3. Thanks Dave. The story of this case is that my friends asked me why Mentor's simulator could not work for UVM-1.2 built-in example, but other vendors could do that without any changes. You know, everyone is going to try the UVM-1.2 example and we are also on the migration way. I also tried to change the gcc to MTI install dir as following changes in Makefile.questa, however I meet the same compile errors. GCC = $(MTI_HOME)/gcc-4.5.0-linux/bin/g++ Do you have any other suggestions? Thanks! cybvgar-nx23:/home/romwang/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence% m Makefile.questa all make -f Makefile.questa BITS=32 dpi_lib make[1]: Entering directory `/home/romwang/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' mkdir -p ../../../../lib /tool/cbar/apps/questa/10.2c/questasim/gcc-4.5.0-linux/bin/g++ -m32 -fPIC -DQUESTA -g -W -shared -x c -I/tool/cbar/apps/questa/10.2c/questasim/include ../../../../src/dpi/uvm_dpi.cc -o ../../../../lib/uvm_dpi.so In file included from ../../../../src/dpi/uvm_dpi.cc:38:0: ../../../../src/dpi/uvm_svcmd_dpi.c: In function 'walk_level': ../../../../src/dpi/uvm_svcmd_dpi.c:45:5: error: 'for' loop initial declarations are only allowed in C99 mode ../../../../src/dpi/uvm_svcmd_dpi.c:45:5: note: use option -std=c99 or -std=gnu99 to compile your code ../../../../src/dpi/uvm_svcmd_dpi.c: At top level: ../../../../src/dpi/uvm_svcmd_dpi.c:57:45: error: expected ';', ',' or ')' before '=' token make[1]: *** [dpi_lib] Error 1 make[1]: Leaving directory `/home/romwang/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' make: *** [dpi_lib32] Error 2
  4. I met following issue in UVM-1.2 built-in example, but it could work well in UVM-1.1d. questasim 10.3c is the same. Are these versions not supporting UVM-1.2? cybvgar-nx23:/home/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence% m Makefile.questa all make -f Makefile.questa BITS=32 dpi_lib make[1]: Entering directory `/home/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' mkdir -p ../../../../lib gcc -m32 -fPIC -DQUESTA -g -W -shared -x c -I/tool/cbar/apps/questa/10.2c/questasim/include ../../../../src/dpi/uvm_dpi.cc -o ../../../../lib/uvm_dpi.so In file included from ../../../../src/dpi/uvm_dpi.cc:38: ../../../../src/dpi/uvm_svcmd_dpi.c: In function 'walk_level': ../../../../src/dpi/uvm_svcmd_dpi.c:45: error: 'for' loop initial declaration used outside C99 mode ../../../../src/dpi/uvm_svcmd_dpi.c: At top level: ../../../../src/dpi/uvm_svcmd_dpi.c:57: error: expected ';', ',' or ')' before '=' token make[1]: *** [dpi_lib] Error 1 make[1]: Leaving directory `/home/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' make: *** [dpi_lib32] Error 2
  5. do set_auto_predict(0) because you are using explicit prediction infrastructure.
  6. Supposed different test could have a little different command line options beside UVM_TESTNAME, then you could also control the timeout via uvm_comandline using "+UVM_TIMEOUT=<timeout>,<overridable>"
  7. Hi, #1. when you call the UVM_REG.write, the bus2reg happens twice. It's correct. 1st happens on uvm_reg_map::do_bus_write (adapter.bus2reg(bus_rsp/req,rw_access) 2nd happens on uvm_reg_predictor::write( adapter.bus2reg(tr,rw) ---- when bus monitor broadcasts the bus transaction (write or read) to uvm_reg_predictor.bus_in, this function will be called and will update the RAL model. #2. Make sure your bus monitor connects to the uvm_reg_predictor.bus_in uvm_analysis_imp well. please also check if the read data is 0 or correct value on the bus of DUT. Try block_obj.reg2.get_mirrored_value(); to check the mirror value.
  8. Update Mentor’s new links to the event. Check it out. http://www.mentorg.com.cn http://www.mentorg.com.cn/aboutus/event_info.php?id=15&s=hyjs http://www.linkedin.com/groups/DVClub-Shanghai-Experiences-Using-UVM-4668056.S.5851471572233117700?view=&gid=4668056&type=member&item=5851471572233117700&trk=eml-anet_dig-b_nd-pst_ttle-cn Posted in Verification Horizons eNewsLetter
  9. DVClub Shanghai Event was posted on Verification Academy@Mentor. https://verificationacademy.com/news/upcoming-verification-events
  10. DVClub Shanghai Event was posted on Cadence website. Please check it out: http://www.cadence.com/cn/cadence/events/Pages/EventDetails.aspx?eventid=139 The tangible banner was added on the main webpage under “最新动态” & “最新活动” section on www.cadence.com.cn
  11. DVClub Shanghai Event was posted on Mentor website. Visit mentorg.com.tw to know more DVClub Shanghai Event! Register and Join us.
  12. Event: Experiences of Using UVM - DVClub Shanghai Date: 28 March 2014 Time: 14.40 to 17.30 (CST) 07.00 to 09.30 (GMT) Organizer: Mike Bartley @TVS Roman Wang @AMD Charles Sun @Topbrian Sponsors: ARM, Cadence, Mentor and Synopsys The next DVClub Shanghai webcast event takes place on Friday, 28th March and will focus on the experience of UVM! Why not register to hear five speakers bringing their own unique perspective: Agenda (CST) 14.40 Arrival and Networking 15.00 Mike Bartley, Test and Verification Solutions - Verification Challange Outlook in 2014 15.30 Uwe Simm, Cadence - UVM1.2: What's Now and What's Next? 16.00 Yuanpeng Su, Synopsys - UVM Best Practices and Debug 16.30 Albert Chiang, Mentor Graphics - UVM, The Next Phase 17.00 Roman Wang, AMD - Are you Suffering to Handle on-the fly Events in Complex UVM Scenarios? 17.30 Close Registration and additional details of the presentations and speakers can be found here https://www.eventbrite.co.uk/e/dvclub-shanghai-28-march-2014-tickets-10200850017 Register the remote way if you could not access locally. DVClub Shanghai is organized by TVS & Topbrain who are committed to making DVClub Shanghai accessible to everyone and you can join the meeting remotely via the Internet or physically in shanghai. If you attend remotely why not do what many other companies do - book a room and invite your colleagues along so you can discuss and debate the topic.
  13. She is nice and I love her, however she bites me everyday.
  14. I believe follow topic could address your problem well. "Resetting Your UVM SystemVerilog Environment in the Middle of a Test — Introducing the UVM Reset Package" http://www.cadence.com/Community/blogs/fv/archive/2014/02/26/resetting-your-uvm-sytemverilog-environment-in-the-middle-of-a-test-_2D00_-introducing-the-uvm-reset-package.aspx
  15. Hi Phil, I think you'd better add the random delay on the iUVC's Driver. (iUVC = Interface UVC) between transaction.. As we know, reg item from UVM REG will be translated to bus item by UVM REG Layering, and iUVC's Driver will drive the bus. UVM REG model is just designed to facilitate productive verification of SW programmable HW. I don't think it's better to implement random on the UVM REG model.
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