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About verif_learner

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  1. is it common not to have uvm_monitor without parameter? For example, the following is a snippet from uvm reference guide. The monitor does not have any parameter while driver has user defined sequence_item as a parameter class master_monitor extends uvm_monitor; virtual bus_if xmi; // SystemVerilog virtual interface bit checks_enable = 1; // Control checking in monitor and interface. bit coverage_enable = 1; // Control coverage in monitor and interface. class simple_driver extends uvm_driver #(simple_item); simple_item s_item; virtual dut_if vif; // UVM automation macros for general components `uvm_component_utils(simple_driver Does this mean that I cannot have multiple instances of monitor with different sequence_item types as class is not type parameterized?
  2. I would like to know what is the recommended place to implement functional coverage 1) non temporal functional coverage - coverpoints I understand these can be implemented in monitors, scoreboards, subscribers, coverage collectors (though I don't know what the last 2 really are) 2) temporal functional coverage - cover directives I understand these can be implemented in interfaces, modules or programs
  3. verif_learner

    AMS modeling

    Thanks you very much.
  4. verif_learner

    AMS modeling

    Hello All, I am new to AMS modeling & I have been going through some study material related to Verilog-A/Verilog-AMS. I have a few questions related to AMS. I hope members here will comment. 1) Is AMS always needed when there is a mix of digital & analog modules in a design. For example, can it not be used for pure Analog modeling when I would like to have abstract analog models? 2) In most of the references, AMS is mentioned as an approach to model design blocks. In my view, AMS has to be used for creating testbench for such blocks. For example, if my design has analog interface then I have to use AMS to apply stimuli to that interface or use AMS to process output from that interface. Thanks,
  5. verif_learner

    How to conrtibute

    Thank you but I don't seem to find any group related to UVM standardization. All I can see are: Interface Technical Committee, Unified Coverage Interoperability Standard, VHDL Technical Committee, Verification IP Technical Committee, Verilog-AMS. Any comments?
  6. Folks, I am new here, so please bear with me if this has been asked before ... May I know how an user like me can influence or contribute to UVM development/definition? For example, sometime back I brought up a topic at OVM and they said that such a thing is being taken care by UVM. Looking at Accelera, I could not make out head and tail as to how the standardization is driven, and who can or cannot contribute. Regards,