uvm_rookie

I was referring to a RO register, not individual field.

In my IPXACT file, I specify a register to be “read-onlyâ€. When I do a read, I do not expect the check function to be turned on, but it did. As a result, my test failed because of the mis-compare. The uvm_reg.svh has the following source code. How come the “if†statement is checking for “WO†rather than “RO†? How would I specify the “UVM_NO_CHECK†in the IPXACT file ? Should a "RO" register implies "UVM_NO_CHECK" ? Here's the "do_check" source code from uvm 1.1a // do_check function bit uvm_reg::do_check(input uvm_reg_data_t expected, input uvm_reg_data_t actual, uvm_reg_map map); uvm_reg_data_t dc = 0; foreach(m_fields) begin string acc = m_fields.get_access(map); acc = acc.substr(0, 1); if (m_fields.get_compare() == UVM_NO_CHECK || acc == "WO") begin dc |= ((1 << m_fields.get_n_bits())-1) << m_fields.get_lsb_pos(); end end

That's exactly what I trying to do, to catch run-away condition .. In case something went wrong with a particular test, it won't be stuck indefinitely and holds up a LSF/server. I will follow the example and setup test specific timeout value in the build phase of each test. Thanks.

I have tests that run minutes, to hours, and up to a week. So, I like to use different timeout for each test. What is the proper way of doing so ?

set_global_timeout is a deprecated feature in uvm1.1a. What is the new way of specifying global timeout ?

Here's the code I use the get_reg_by_offset mybus_rdb_pkg::mybus_am model; uvm_reg_map maps[$]; uvm_reg current_reg; ... ... model.get_maps(maps); current_reg = maps[0].get_reg_by_offset(reg_addr, (rw.kind == UVM_READ)); I was not able to use get the get_mem_by_offset to work. My workaround is the following : uvm_mem uvmmems[$]; model.get_memories(uvmmems); foreach (uvmmems) begin base_addr = uvmmems.get_address; if ((rw.addr >= base_addr) && (rw.addr <= base_addr + uvmmems.get_size() - 1)) 1)) current_mem = uvmmems; end

I am trying to use get_mem_by_offset to identify the memory name by providing the offset address. I could not get it to work as the function return null. uvm_reg_by_offset works fine for me. Anyone has any ideas ? Note: I am using both uvm1.1 and uvm1.1a

What is the usage model for uvm_config_db::wait_modified ? Can anyone provide an example ?

What is the proper way to specify objection inside a sequence ? Do I need to add objection code in both regular sequences and virtual sequences ? Method 1 : virtual task pre_body(); uvm_test_done.raise_objection(this); endtask : pre_body virtual task post_body(); uvm_test_done.drop_objection(this); endtask : post_body Method 2: virtual task pre_body; if (starting_phase != null) starting_phase.raise_objection(this, "Starting seq"); endtask: pre_body virtual task post_body; if ((get_parent_sequence() == null) && (starting_phase != null)) starting_phase.drop_objection(this, "Ending seq"); endtask: post_body

Is there a way to parameterize an UVM UVC ? The UVC is designed to have a MAX_LANES = 64. For a particular testbench, I want to configure this UVC to only has MAX_LANES=8. The following code doesn't work : class demo_tb extends uvm_env; `uvm_component_utils(demo_tb) bss_uvc_frmbuf_env #(.MAX_LANES(8)) frmbuf_env; function new (string name, uvm_component parent); super.new(name, parent); endfunction : new extern virtual function void build_phase(uvm_phase phase); endclass : demo_tb function void demo_tb::build_phase(uvm_phase phase); super.build_phase(phase); frmbuf_env = bss_uvc_frmbuf_env #(.MAX_LANES(8)) ::type_id::create("frmbuf_env", this); endfunction : build_phase I got the following error : ncelab: *E,TYCMPAT (./examples/demo_tb.sv,74|68): assignment operator type check failed (expecting datatype compatible with 'specialization of class bss_uvc_frmbuf_env' but found 'class bss_uvc_frmbuf_env' instead). ncelab: *F,CUPKGE: Elaboration cannot proceed: design unit 'demo_base_test' uses a SystemVerilog class 'demo_tb' for which an elaboration error occurred.

I used the ovm2uvm.pl to convert my OVM to UVM ... I was using global_stop_request() in my test run_phase. Now, I need to use the following objection code : virtual task run_phase(uvm_phase phase); phase.raise_objection(this,"Start run phase"); .... .... phase.drop_objection(this,"Start run phase"); // global_stop_request(); endtask : run_phase I didn't need to use +UVM_USE_OVM_RUN_SEMANTIC

Hi, that code is a built-in UVM code. I tried to switch off the message by using UVM_NO_DEPRECATED, but I got all kind of compilation error. So, I guess I can down to choice 1 ....

I got the following UVM DEPRECATED Warning. The problem is in the library file uvm_sequence_builtin.svh. Do I need to compile with UVM_NO_DEPRECATED ? ---------------------------------------------------------------- UVM-1.0p1 © 2007-2011 Mentor Graphics Corporation © 2007-2011 Cadence Design Systems, Inc. © 2006-2011 Synopsys, Inc. ---------------------------------------------------------------- UVM_WARNING /uvm/src/seq/uvm_sequencer_base.svh(1390) @ 0.000ns: uvm_test_top.testbench.tx_uvc.tx_agent.sequencer [uVM_DEPRECATED] Registering sequence 'uvm_random_sequence' with sequencer 'uvm_test_top.testbench.tx_uvc.tx_agent.sequencer' is deprecated. UVM_WARNING /uvm/src/seq/uvm_sequencer_base.svh(1390) @ 0.000ns: uvm_test_top.testbench.tx_uvc.tx_agent.sequencer [uVM_DEPRECATED] Registering sequence 'uvm_exhaustive_sequence' with sequencer 'uvm_test_top.testbench.tx_uvc.tx_agent.sequencer' is deprecated. UVM_WARNING /uvm/src/seq/uvm_sequencer_base.svh(1390) @ 0.000ns: uvm_test_top.testbench.tx_uvc.tx_agent.sequencer [uVM_DEPRECATED] Registering sequence 'uvm_simple_sequence' with sequencer 'uvm_test_top.testbench.tx_uvc.tx_agent.sequencer' is deprecated.

UVM1.0 has an ubus example. One of the test has the following code. Instead of using set_config_string, we need to use uvm_config_db .. We do this in the build phase of this test class. How come we need to use "sequencer.run_phase", instead of "sequencer.build_phase" ? // Read Modify Write Read Test class test_read_modify_write extends ubus_example_base_test; `uvm_component_utils(test_read_modify_write) function new(string name = "test_read_modify_write", uvm_component parent=null); super.new(name,parent); endfunction : new virtual function void build_phase(uvm_phase phase); begin uvm_config_db#(uvm_object_wrapper)::set(this, "ubus_example_tb0.ubus0.masters[0].sequencer.run_phase", "default_sequence", read_modify_write_seq::type_id::get()); uvm_config_db#(uvm_object_wrapper)::set(this, "ubus_example_tb0.ubus0.slaves[0].sequencer.run_phase", "default_sequence", slave_memory_seq::type_id::get()); // Create the tb super.build_phase(phase); end endfunction : build_phase endclass : test_read_modify_write

I use the ovm2uvm conversion script to convert my OVM OVC to UVM UVC. I notice that the OVM has ovm_base_pkg.sv but UVM only has uvm_pkg.sv. What happened to the ovm_base_pkg.sv ? We don't need this file anymore ?