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IChip

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  1. When reset occurs, why not try to stop writing transactions to comparator?
  2. How do you run your sequence? Are you sure starting_phase is not a null handler?
  3. Thanks Erling. In my knobs class, there are lots of config variables used for different sequences.And the knobs need to be visiable in all sequences.
  4. I want to share the config bewteen 2 different type of sequences. How they were executed is based on the config and there may have lots of such sequences. Thanks
  5. Thanks Erling & cdnmcgrath. Your comments are very helpfull for me. And to avoid this problem, then I try several ways: (1) locate the knobs in the sequence or set up the my own p_sequencer before randomization. I use uvm_top.find("virtual_sequencer") to get the handle of virtual sequencer in pre_randomize(). So the knobs is also got even where ever it is placed. (2) try a nested sequence,like this: class virtual_sequence_top extends uvm_sequence; `uvm_declare_p_sequencer(virtual_sequencer) task body(); virtual_sequence vseq0; virtual_sequence vseq1; `uvm_do_with(vseq0,{vseq0.num==p_sequencer.knobs.num;}) //constraint solved after p_sequencer is set up `uvm_do_with(vseq1,{vseq1.num==p_sequencer.knobs.num;}) endtask endclass Thanks a lot
  6. Hi experts, I want to add knobs/config object in virtual sequencer to control sequence constraints. But some errors are not expected, which need your helps. Here is the pieces of codes: --------------------------------------------------------------------------------- class virtual_sequencer extends uvm_sequencer; knobs kb;//assume it configed in an test endclass class virtual_sequence extends uvm_sequence; `uvm_declare_p_sequencer(virtual_sequencer) rand bit[31:0] num; constraint cstr { num==p_sequencer.kb.num;} endclass ---------------------------------------------------------------------------------The runtime error is that virtual_sequence failed to be randomized because p_sequencer.kb.num is not allocated.Here is the questions: I guess when virtual_sequence is ran to do a randomization,the p_sequencer is still not assigned and it is null, right? Any better ways will be appreciated and thanks in advance.
  7. In pre_body() host_seqs is an null until it's created in body().
  8. Hi experts, I found a uvm_error in my tb based on uvm-1.1b as below: And there is a forever block in seqA body(), which will send items to driver all the time. how can i stop such sequence which run on agt.main_phase, when main_phase start to jump the next phase??? It does not work using the following. function void phase_ready_to_end(uvm_phase phase); 302 static int count = 0; 303 count++; 304 if(phase.get_name()=="main") begin 305 if(count>=20) begin 308 [COLOR="red"]agtA.sequencer[/COLOR].stop_sequences(); 309 end 310 end 311 endfunction : phase_ready_to_end Thanks in advance
  9. As i known, every sequence has a variable called starting_phase, in which a sequence is started. I'm not sure this could hep. Maybe you can try to use this variable to indicate sequence is started from main_phase or from run_phase.
  10. IChip

    generate block

    Thanks aji.cvc for your useful notes. And I should add the line below in my workaround. foreach(x_agents) x_agents.set_i(xxx);
  11. IChip

    generate block

    Thanks, Dave & mea1201. It works for me. for(int n = 0; n<CLIENT_LEVEL_NUM; n++) fork automatic int j = n; forever begin ...... end join_none I have another workaround and maybe non-standard. class A extends uvm_component; int i; task run_phase(uvm_phase phase); forever begin e[i].wait_on(); seq.start(agents[i].sequencer); e[i].reset(); end endtask endclass : a A x_agents = new[NUM];
  12. Hi experts, I want to write several forever blocks dynamically. Just like: fork forever begin e[0].wait_on(); seq[0].start(agents[0].sequencer); e[0].reset(); end forever begin e[1].wait_on(); seq[1].start(agents[1].sequencer); e[1].reset(); end ... joinThen I want to use generate block to replace mass codes above and make it configurable. for(genvar i=0 ;i< NUM; i++) forever begin e[i].wait_on(); seq[i].start(agents[i].sequencer); e[i].reset(); end But compile error: Verilog keyword 'genvar' is not expected to be used in this context. How can i use generate block in a class context?? Thanks
  13. Thanks Simulation ended at time 10.
  14. Hi dave, May I ask another question? When use the red line below, simulation will be ended at time 2. In this case, why is run_phase block also killed? Thanks. task run_phase(uvm_phase phase); phase.raise_objection(this); #10; phase.drop_objection(this); endtask task delay_to_end(uvm_phase phase); #1; `uvm_info(get_name(),$sformatf("Now to end %s...",phase.get_name()),UVM_LOW) phase.drop_objection(this); endtask function void phase_ready_to_end(uvm_phase phase); static int done = 0; if(done)return; [COLOR="Red"] //if(phase.get_name == "main")begin[/COLOR] if(phase.get_name == "run")begin `uvm_info(get_name(),"Not yet to end...",UVM_LOW) phase.raise_objection(this); fork begin #1; this.delay_to_end(phase); done = 1; end join_none end endfunction
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