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ljepson74

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Everything posted by ljepson74

  1. Join a casual gathering of SystemVerilog users. 7pm. Wednesday 20th. Patxi's in San Jose. 3350 Zanker Road. SJ, CA 95134. (If joining us, please reply on the meetup website indicated below, as this is not a reserved room, but just some tables pulled together, with everyone covering their own bill.) Happy Holidays
  2. What tools exist for SystemVerilog/UVM linting? I recently evaluated AMIQ's Verissimo (which I liked). However, I'd like to know what else is out there.
  3. What is the intended use case for 'starting phase'?** Is it so that a test writer can determine if a sequence has been started, so they might conditionally do something like raising an objection? thanks **I use 'starting phase', instead of starting_phase, because that seems to be how it is referred to now (perhaps because it is protected now).
  4. UVM Phases: end_of_elobration

    Regarding: I would not say that a phase is required and I would not say it is not required. The uvm phases will be passed through in succession, as a simulation runs. I would simply say "they will happen". In a normal UVM flow, there is no way to make a phase not happen**. I think the question you want to ask is whether you, a user, or a test/testbench, needs to use the end_of_elaboration_phase (or any phase). The answer to that, is no. If you do not specify a function or task for the specific phase (and raise an objection if necessary), it will simply pass through. italiya listed some things that might be done in that phase, but as pointed out, could be done in other phases as well.*** uvm phases, for the most part, are artificial sections of time, to help developers organize code more consistently. Silly, off-the-cuff analogy: Everyone on this forum decides to run their lives a certain way, on a certain schedule. 6am-7am: wake, eat_breakfast, empty_garbage 10am-11am: go_to_work 11am-2pm: 2pm-4pm: cigar_break 9pm-10pm: go_home, eat_dinner, sleep When you visit italiya, you'll know that you can expect breakfast in the time "6am-7am". You'll know the rules of his home. Italiya could decide to eat_breakfast in the time "11am-2pm" instead, or to not eat_breakfast at all (like not using the end_of_elaboration_phase), and things will be fine, but it might cause confusion for his guests who expect the above schedule. In verification the uvm phase guidelines should help us all more quickly understand each others' tests and testbenches. Just as Italiya cannot go_to_work before wake, there are certain things in our testbenches that must happen in a certain order. For example, we must build/instantiate our testbench parts, before we generate stimulus or do anything else. The structuring of phases help us to keep that order. **Well, certainly one could choose to end a test in any phase, before all phases are completed, or to phase jump. But, in a typical flow, all phases will happen. ***Besides time-consuming items being required to happen in the run_phase (or it's sub phases), and besides building of components before the run_phase (?), I am not sure what else is restricted to a certain phase or group of phases. An important distinction that was never so clear to me when I started is that the run_phase and it's sub phases are tasks (which can consume time), the other phases are functions (which cannot consume time). I'm prepared for clarifications/corrections from others, but that's my understanding. //This forum tool seems to be adding interesting colors to this post based on my use of ' and formatting buttons.
  5. A backslash can be used to extend a string literal onto the next line if "the new line is immediately preceded by a \ (backslash)." Section 5.9 of 1800-2012.pdf, the SystemVerilog LRM I don't think I have ever been able to get this work and w/o looking I seem to recall it has been in Verilog/SystemVerilog for a while. Can someone tell me if vendors support this and perhaps correct the code below on edaplayground? example from LRM: $display("Humpty Dumpty sat on a wall. \ Humpty Dumpty had a great fall."); See example here (on Sept 29, urls below are updated in response to Tudor comment below. thx.): http://www.edaplayground.com/x/4Tyw https://www.edaplayground.com/x/4Tyw //if the above does not work, try this one, with https://
  6. Yes, thanks Dave. (I shouldn't assume everyone I've seen on here monitors all the threads.) Feedback from Victor (the creator of edaplayground) on the edaplayground forum:
  7. Doulos/Victor, any thoughts? Is your editor causing mischief and adding characters at the ends of lines? Dave, I see your point now. i.e. In edaplayground the error message seems to point to a space after the backslash. Thanks.
  8. EDAboard.com ? Is that a typo? You just mean my text editor, right? I confirmed that there is no extra character at the end of the line. (Note: the links above have been fixed.)
  9. Thanks, Tudor and Dave. *) I updated the urls, per Tudor comment. *) Aldec and Mentor simulators were the two that I did not use. I now tried Aldec on edaplayground and see that it works. Unfortunately, with regards to this SV feature, I'm not using either of these simulators. Can anyone confirm that neither Cadence nor Synopsys support this? (Well, I guess I've figured out that they don't, now that I have witnessed at least one simulator support it. Aldec's.) Thanks.
  10. How can I check which VCS version I am using, from a Linux command line? I don't want to run a sim to find this information. I am looking for smthg like "irun -version", but for VCS. Pre-post discovery: It looks like "vcs -help", among other things, shows the compiler version. Afaik, the compiler version and simulator version are the same. Right? Normally, I wouldn't ask that, but I see/know that some tools (or subsections of tools) don't move in lock-step for versions (like simulators and waveform viewers). (Posting here because I didn't easily find this in VCS documentation and had SolvNet problems, and I find it better not to ask non-proprietary questions where the answer is available to the public.)
  11. Q1) I'd like confirmation that the following waits for a posedge of clk are identical. (The code it refers to is far below.) 1) @(posedge my_play_if.clock); or @(posedge clk); 2) @(my_play_if.cb1); Q2) I'd also like to confirm that input and output clocking_skew of a clocking block have no effect on the inputs of the interface. They only affect the inputs and outputs of that clocking block. I'm pretty confident about both of these and the SystemVerilog LRM seems clear, but I want to confirm while I am cleaning up some inherited code which is not currently working. Reference: SystemVerilog Standard 1800-2012.pdf, Section "14. Clocking blocks" Below is some sample code I was hacking around with. //Interface, clocking blocks, and waiting for clock edge interface play_if(input bit clock); clocking cb1 @(posedge clock); default input #2 output #2; //clocking_skew is irrelevant to interface inputs, right? endclocking endinterface module top; bit clk; play_if my_play_if(.clock(clk)); always #5 clk=~clk; initial begin $monitor($time," clk=%1b",clk); clk=1; #100 $finish; end task tclk(); $display($time," pre-clk"); @(posedge my_play_if.clock); $display($time," post-clk"); endtask task tcb1(); $display($time," pre-cb1"); @(my_play_if.cb1); $display($time," post-cb1"); endtask initial begin #23; $display($time," --------------START"); tclk(); @(posedge my_play_if.clock); tclk(); #3; tcb1(); tcb1(); @(posedge my_play_if.clock); tcb1(); tclk(); tcb1(); #3; @(posedge my_play_if.clock); $display($time," --------------FINISH"); end endmodule : top
  12. Thanks, Dave. To be clear, as I understand, "synchronize that process to the clocking block event" in this case means a call to @(my_play_if.cb1); Good. I'm moving to use such calls for the advancement of time (mostly in drivers and monitors/collectors), instead of calls like @(posedge my_play_if.clock); or @(posedge clk);. Can you provide a pseudo-code example of "interacting with clocking block inputs ##0 delays"? As I understand**, if there is a default clocking_block (and only if), we can use cycle delays (i.e. ## integral_number) and that will cause a wait for the specified number of clocking events (even if the first is in the current time step). But as long as the input clocking_skew specifies some time before the clocking event, I don't see where a problem would arise by using ##0;. Note: Outside of assertions, I don't think I've ever used cycle delays. Also, I don't use default clocking_blocks, for better or worse. ** 1800-2012.pdf Section "14.11 Cycle delay: ##" Note: I've updated the original post to highlight the querys with "Q1)" and "Q2)".
  13. How to check VCS version number?

    Thanks, Alan. That wasn't it, but Synopsys got back to me: For VCS: vcs -ID For Verdi waveform viewer: verdi -envinfo | more
  14. How can I use "randomize() with" along with "inside", on the same line? Below is some code that solves the problem using >= and <=, but I'd like to use "inside". module top; class aclass; int index; function void get_latency; //assert (randomize(index) with {index inside {[1:5]}}) else begin //WHAT IS THE PROPER SYNTAX? //assert (randomize(index) inside {[1:5]}) else begin //WHAT IS THE PROPER SYNTAX? assert (randomize(index) with {index<=5; index>=1;}) else begin //WORKS $display("ERROR: We failed!"); $finish; end $display("RESULT: index=%0d",index); endfunction endclass initial begin aclass a_class=new(); a_class.get_latency(); $finish; end endmodule I often grapple with the "randomize with" syntax, getting confused with squiggly brackets and semicolons, and refer to the LRM. (Any tips that will stick in my head are welcome.)
  15. randomize() with inside syntax

    Thanks a lot, dave_59. Seeing those two (the inline and the constraint block) lined up like you did will help this stick in my head that they are the same syntax.
  16. Is it possible to randomize a string without home-brewing a function to do it? Can only integral data types be randomized, hence not strings? How much memory is allocated when a string is declared? Is a string just a dynamic array 'underneath'?
  17. Yesterday, I learned that when randomize is called, all active constraints in the scope must be met ... even if you are passing a specific member as an argument to the randomize call. i.e. If you try to randomize a specific class member by passing it to the randomize call, like this: randomize(var2), all constraints in the scope of the randomize must still be met, even if they have nothing to do with the member being randomized. ***Someone please jump in if I phrased that poorly or am incorrect. In the below example there are two variables and a constraint on one. Uncommenting the line that causes the constraint on var1 to be violated will cause the later call to randomize to fail, even though it is passed an argument (var2) that has nothing to do with var1. class showit; rand int var1; rand int var2; constraint c_1 { var1<100; } endclass ////////////////////////////////////// module top; showit showit; initial begin showit=new(); //showit.var1=101; UNCOMMENT ME, PLEASE FOR FAIL as_myassert : assert(showit.randomize(var2)) begin $display("\n********** Victory : var2=%0d var1=%0d \n",showit.var2, showit.var1); end else begin $display("\n********** Defeat : var2=%0d var1=%0d \n",showit.var2, showit.var1); end end endmodule : top Pass result: ********** Victory : var2=-1424717967 var1=0 Fail result: ********** Defeat : var2=0 var1=101 I now understand randomize better. I had thought that only the constraints that pertained to the items being randomized were relevant.
  18. Awesome. +2pts for Logger. Thanks a lot, that is great to know about. I'll be using it. re: Section 18.5.14 Soft constraints (from 1800-2012.pdf)
  19. Consider the following code and the assertion to check for unknown data. If the code will change so that there will now be an array of valids and datas, what is the best way to change the assertion, so that for each valid, the corresponding data is checked.? Can I do it one line? (I had been considering using a generate statement around it.) module top; bit clk; logic write_valid; logic write_data; always clk = #5 !clk; initial begin clk=0; write_valid=0; #7; write_valid=1; #100; $finish; end as_showme : assert property (@(posedge clk) disable iff (!write_valid) (!$isunknown(write_data)) ) else begin $display("*** ERROR. write_data was unknown. ***"); end endmodule
  20. Tudor/Tinku, Thank you very much. I had considered these following variations (and will now make doubly sure they're clear in my mind): //i) disable iff (write_valid) !$isunknown(write_data) //use disable iff for asynchronous disabling //ii) write_valid |-> !$isunknown(write_data) //Recommended //iii) !(write_valid && $isunknown(write_data)) //***See below I had not thought about synchronicity with regards to disable iff, so thanks a lot for enlightening me, Tudor. (***And in another post we discussed implication versus logical AND. http://forums.accellera.org/topic/5407-overlapped-implication-vs-logical-and-vs/ ) , ... but the focus of the topic, which I may not have presented clearly enough was what Tinku showed. I was hoping there was some way to avoid using a generate, but that solution seems very clear. Thank you for shedding light on parts of the example I hadn't even thought much about yet.
  21. I needed to step thru an enum in a testbench today. As it took me a while to figure out how to do it, I post a small example here. I want to do it without making any assumptions of the values of the enums (values are the default type of int, in this case). Reference: SystemVerilog doc "1800-2012.pdf" Section 6.19 Enumerations module top; //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek; //to show default assignments typedef enum {alpha, beta, gamma, delta, epsilon} greek; greek letters2; initial begin $display("****** Walk thru an enumeration example. ***********"); for (greek letters=letters.first(), int walk=0; walk < letters.num(); letters=letters.next(), walk++) begin $display(" %0d *** %0s", letters, letters.name); end end endmodule : top Output: ****** Walk thru an enumeration example. *********** 0 *** alpha 1 *** beta 2 *** gamma 3 *** delta 4 *** epsilon I'm also posting here, because when I am trying to remember how to do something, I find it often easier to find my postings online than an example in my own code. I thought I did this nicely with a foreach loop, but cannot find it, so may be imagining it. I was not keen on having to use variable walk. If someone can show me how to do this with a foreach loop or without using an extra variable, like I did with "walk", please do. Noted failures: for (greek letters=letters.first(); letters!=letters.last(); letters=letters.next()) begin //shows only 0-3 for (greek letters=letters.first(); letters<=(letters.num()-1); letters=letters.next()) begin //neverending loop
  22. When used in a coverpoint, what is the difference between overlapped implication and logical AND? |-> vs. && cp_test : cover property ( @(posedge clk) disable iff (!resetn) A |-> B ); cp_test : cover property ( @(posedge clk) disable iff (!resetn) A && B ); ? A colleague asked me. It seems to me they are the same and the logical AND is more readable.
  23. Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking. case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share case2) XYZ testbench. the same case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VHDL. Or, we can bind the sv interface to the ABC-XYZ connection, to reuse the protocol checking of that interface. Without using a macro or `include of the protocol checking code, I'd like to just have a package or some place where we store the protocol checking code and can reuse it, whether in an sv interface, or a module which we bind to the VHDL. Looking into this, and researching putting assertions into packages, I discovered checkers. Hence this line of questioning. Please share your thoughts and experience.
  24. Nhat, Can you provide more details in your question? You want a monitor and scoreboard to be able to check that suspend and resume operations occur correctly for a flash memory design. Correct? I would guess that few people on this forum are familiar with flash memory controller design and with those operations. I am not familiar with them. How about if you separate the application specific part (flash controller) of your question from the UVM/SV part? I think the flash part of the question confuses and deters people from responding. Your question was very short and provided little information. Look at other questions on this forum. Read this posting about asking good questions: https://www.biostars.org/p/75548/. We're all in a rush somtimes and then ask questions quickly and with little information. I certainly do. And sometimes we can review and review and add more and more information to a question (gold-plating it, people say - making it perfect), and the people that ultimately respond to it only needed a small part of that, and a lot of time is wasted. I certainly can take forever to compose a question/response, sometimes. It's tough sometimes to know how much time and detail to put into a question. I think that in this case more detail in the question would have gotten you an answer, already. More information helps others determine the experience level of the person asking the question - resulting in a more appropriate answer. Would it be correct to rephrase your question like this? *I am new to UVM. *I must verify that two types of multi-cycle operations occur correctly, but am unsure of how to best do it. *The operations are i) suspend of either a program or erase command ii) resume of either a program or erase command. *Can someone help me determine how to verify this? Or, maybe you are not new to UVM. If so, share what you have already tried. Let's make the problem smaller. If we only wanted to verify that a bus changes from 0x04 to 0x44, using a monitor and scoreboard, can you do that? Or should we start earlier in an explanation?
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