ljepson74

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1. walk thru an enumeration

I needed to step thru an enum in a testbench today. As it took me a while to figure out how to do it, I post a small example here. I want to do it without making any assumptions of the values of the enums (values are the default type of int, in this case). Reference: SystemVerilog doc "1800-2012.pdf" Section 6.19 Enumerations module top; //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek; //to show default assignments typedef enum {alpha, beta, gamma, delta, epsilon} greek; greek letters2; initial begin \$display("****** Walk thru an enumeration example. ***********"); for (greek letters=letters.first(), int walk=0; walk < letters.num(); letters=letters.next(), walk++) begin \$display(" %0d *** %0s", letters, letters.name); end end endmodule : top Output: ****** Walk thru an enumeration example. *********** 0 *** alpha 1 *** beta 2 *** gamma 3 *** delta 4 *** epsilon I'm also posting here, because when I am trying to remember how to do something, I find it often easier to find my postings online than an example in my own code. I thought I did this nicely with a foreach loop, but cannot find it, so may be imagining it. I was not keen on having to use variable walk. If someone can show me how to do this with a foreach loop or without using an extra variable, like I did with "walk", please do. Noted failures: for (greek letters=letters.first(); letters!=letters.last(); letters=letters.next()) begin //shows only 0-3 for (greek letters=letters.first(); letters<=(letters.num()-1); letters=letters.next()) begin //neverending loop
2. overlapped implication vs logical AND. |-> vs. &&

When used in a coverpoint, what is the difference between overlapped implication and logical AND? |-> vs. && cp_test : cover property ( @(posedge clk) disable iff (!resetn) A |-> B ); cp_test : cover property ( @(posedge clk) disable iff (!resetn) A && B ); ? A colleague asked me. It seems to me they are the same and the logical AND is more readable.
3. SystemVerilog checkers. simulator support. usage in a UVM environment

Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking. case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share case2) XYZ testbench. the same case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VHDL. Or, we can bind the sv interface to the ABC-XYZ connection, to reuse the protocol checking of that interface. Without using a macro or `include of the protocol checking code, I'd like to just have a package or some place where we store the protocol checking code and can reuse it, whether in an sv interface, or a module which we bind to the VHDL. Looking into this, and researching putting assertions into packages, I discovered checkers. Hence this line of questioning. Please share your thoughts and experience.

6. uvm_config_db and hierarchical access

Yes. And I suppose there is no reason it should be a uvm_component - I am not using phases or anything particular to uvm_components here. I am probably muddying the waters by having "config" in the name, and will do some more reading today to understand normal UVM configurations. "xyz_access_point". Probably that is a better name for what I do here than xyz_config. xyz is the module being tested in this case, and this singleton class below is used to provide a means to use the static operator, ::, to access elements from anywhere in the testbench. ex: xyz_config::m_id_state.move_some_id Is it a "a full STATIC configuration singleton", you ask? I'm not fully sure what that means, but see below. // CLASS: xyz_config // //This should be a singleton and serve as a central point for others to access globally used objects. //This is likely not a good style. It is certainly not agreed upon. Discuss. // class xyz_config extends uvm_component; `uvm_component_utils(xyz_config) static xyz_env m_env; static id_state m_id_state; static delay_ctl m_delay_ctl; function new(string name="xyz_config", uvm_component parent=null); super.new(name, parent); endfunction extern static function void set_env_handle(input xyz_env handle); extern static function void set_id_state_handle(input id_state handle); extern static function void set_delay_ctl_handle(input delay_ctl handle); endclass : xyz_config //-- // FUNCTION: set_*_handle // // These functions receive and set handles to their respective objects // function void xyz_config::set_env_handle(input xyz_env handle); m_env=handle; endfunction : set_env_handle function void xyz_config::set_id_state_handle(input id_state handle); m_id_state=handle; endfunction : set_id_state_handle function void xyz_config::set_delay_ctl_handle(input delay_ctl handle); m_delay_ctl=handle; endfunction : set_delay_ctl_handle c4brian, you lost me on the jealous part. What do the YES and NOs mean? Those are uses for config objects (whether they use config_db or not) or smthg?
7. good technique to generate a random delay?

Regarding c4brian comment: You summed it up very well. All of the 'pulling' would happen in one centralized file. I'll start a new thread about this so as not to change the topic here, where I think you might add other comments and thoughts from our side discussion. (new thread: http://forums.accellera.org/topic/5234-uvm-config-db-and-hierarchical-access/ ) --- "tudor has mentioned this before, but "singleton" just means... there's 1, right?" Yup.** (There could be some code inside the class to restrict instantiation of the class to one object (as I recall), but I just instantiate it once.) --- Regarding bhunter1972 comment: I've heard (and read, I think) that sequences should not have any concept of time. This is smthg I need to explore more. --- I've totally mixed you two Brians up in the past on this forum. It's nice to have this thread appear as a way to straighten things out in my mind. **Tudor also got me thinking about composition vs. inheritance more.

9. uvm_builtin_reg_test_seq & default sequences

I am trying to run the uvm builtin register sequences. I seem to have broken our usage of them in porting code from a previous project. Q1: In the past, we've started them as default sequences. Is there any way to have an error/warning appear if a 'set', such as the below, is never utilized (or 'get'-ed)? uvm_config_db#(uvm_object_wrapper)::set(this, "*.m_reg_agent.m_seq_reg.main_phase", "default_sequence", uvm_builtin_reg_test_seq::type_id::get()); I've added uvm_top.print_topology(); and uvm_config_db::dump(); and it seems the ::set should be working, but nothing is starting. Q2: Are builtin (base class) sequences automatically "::created" somehow/somewhere? (Creation/new-ing is still necessary when you setup a default sequence, right? Or is there some magic singleton-ness that happens?) Q3: My error of the moment is as follows. Your thoughts are appreciated. UVM_FATAL @ 39990: reporter@@seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in seq always@(posedge clk), ljepson74
10. SystemVerilog checkers. simulator support. usage in a UVM environment

2+ years later ... Does anyone have new information on checker support and/or best practices for usage?
11. how to display UVM_VERBOSITY

How do I display the name string of the UVM_VERBOSITY? I have been using this to report the verbosity level, but it returns an int. m_rh.get_verbosity_level() How would you display the enumerated name as opposed to the enumerated value? I'm looking at section "6.19 Enumerations" of the LRM (1800-2012.pdf) and close, but not there yet, so I punt this question out into the ether. .name() seems like it should be in there somewhere.
12. uvm_sequence_base kill on virtual sequence

I learned .... uvm_sequencer has the following two functions: function void kill_sequence ( uvm_sequence_base sequence_ptr) virtual function void stop_sequences () Tells the sequencer to kill all sequences and child sequences currently operating on the sequencer, and remove all requests, locks and responses that are currently queued. This essentially resets the sequencer to an idle state. Stop_sequences While this is different from my original post, and I have not tried either yet, these look useful for what I was doing and will probably allow me to replace the function I added to the virtual sequence, so that it can terminate its child sequences. What I was doing was trying to kill all activity in/from testbench, so that I can reset at a random time in the middle of a test. (I am specifically avoiding phase jumping.) (I learned this from interviewing a candidate today and doing some follow-up research. It's great to learn something in an interview.)
13. uvm_sequence_base kill on virtual sequence

When using uvm_sequence_base's kill on a virtual sequence, will it kill child sequences? It seems to me that it will not, but I am unsure and have not explored this much, yet. Looking briefly at the UVM base class, I'm guessing that a virtual sequence should have its own function to terminate child sequences. ----- update: I added a function in the virtual sequence to terminate child sequences and everything is working fine.
14. named event to trigger between class and module

We (as an industry) normally use virtual interfaces to communicate between the module 'world' and the class 'world' of SystemVerilog. Right?** Can anyone comment on the use of events (named events) for class<-->module communication? Good? Bad? Gothchas? Scenario: A test wants to send a signal (trigger) to the top (where the DUT is instantiated). Creating a 1b interface to transmit this trigger seems like overkill, but that is what I did. I had some trouble triggering on an event between module and class. Hierarchy problems. I did not try passing the event thru the config_db - if that even makes sense (is possible). **Correct me if I'm wrong, but that's the way I see it. I'm sure the UVM base class has a sea of code that I don't understand.
15. named event to trigger between class and module

We hacked around with this tonight @ http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley Here is the code. I think the uvm added to some confusion for me. Maybe tomorrow I'll replace the interface I used. // From SVSC meetup, 2015 July 20 // Some code we hacked around with. // Trying to get event to trigger between module and class. // Play: // Swap A1 and A2. // Switch the locations of the initial blocks, so order compiler // encounters them differs. // Comment out/in B1, to adjust the triggering of the event class event_holder; event class_e; function new(); \$display(" pre trigger."); ->\$root.top.top_e; //or even just ->top.top_e; \$display(" post trigger."); endfunction endclass : event_holder module top; event top_e; initial begin event_holder m_event_holder; \$display(" Start ** ** **."); #1; //B1 m_event_holder=new(); #55; //->top_e; end initial begin \$display(" pre event."); @top_e; //A1 //wait(top_e.triggered); //A2 \$display(" post event."); end endmodule
16. How to get virtual interface in sequence

Praneeth, Try something like this in the sequence: virtual my_if m_my_vif; if (! uvm_config_db#(virtual my_if)::get(uvm_root::get(),"*","somestring",m_my_vif)) `uvm_fatal("config_db"," vif connect failed") Elsewhere, you'd need to have added the handle to the config_db, like so: my_if m_my_if; uvm_config_db#(virtual my_if)::set(uvm_root::get(),"*", "somestring", m_my_if); I haven't compiled this to check for typos. Feedback from gurus welcome. Particularly, I'd like to hear thoughts on having a clock in a sequence.
17. iff usage (as a mechanism for waiting)

Thanks a lot, Dave. Aside: For non-English speakers, my above usage of the word "tine" (a prong or sharp point, such as that on a fork) was an attempt at some fork humor.
18. iff usage (as a mechanism for waiting)

I happened across the following code. @(m_vif.smp_cb iff (m_vif.smp_cb.xyz_enable) ); To get to the crux of my question, let's consider it to be the below code. I don't think I've dropped anything relevant with this change (but I post both, b/c I have dropped important info with my edits in the past). @(posedge clk iff (xyz_enable) ); Q) How should the above line behave? How would you read that line aloud? 1) "Wait for a posedge of clk, if and only if xyz_enable is true." //That's how I read it, but that is incorrect. 2) "Wait for posedges of clk until xyz_enable is true." //This is correct. My thought was that when xyz_enable==0, it would just 'fall through' and there would be no wait for a posedge of clk. i.e. if(xyz_enable) @(posedge clk); Can someone help me read that line as a descriptive sentence? Here is some test code: module top; logic clk; int count=0; initial clk=0; always #1 clk = ~clk; initial begin \$display(\$time," ************* START"); repeat (10) @(posedge clk); fork begin repeat(33) begin \$display(\$time," Tine1: waiting for posedge clk. count=%0d",count); @(posedge clk); count++; end end begin \$display(\$time," Tine2: waiting for count=10"); @(posedge clk iff (count==10)); \$display(\$time," Tine2: waited for count=10. count=%0d",count); end join_any \$display(\$time," ************* END"); \$finish; end endmodule Results: 0 ************* START 19 Tine1: waiting for posedge clk. count=0 19 Tine2: waiting for count=10 21 Tine1: waiting for posedge clk. count=1 23 Tine1: waiting for posedge clk. count=2 25 Tine1: waiting for posedge clk. count=3 27 Tine1: waiting for posedge clk. count=4 29 Tine1: waiting for posedge clk. count=5 31 Tine1: waiting for posedge clk. count=6 33 Tine1: waiting for posedge clk. count=7 35 Tine1: waiting for posedge clk. count=8 37 Tine1: waiting for posedge clk. count=9 39 Tine1: waiting for posedge clk. count=10 39 Tine2: waited for count=10. count=10 39 ************* END Thanks, for any feedback.
19. iff usage (as a mechanism for waiting)

I found that even if the condition is true from the start, as it is here... int count=10; ... @(posedge clk iff (count>=10)); a single posedge clk will be waited for.
20. waiting in a sequence

*, Is one of these ways to have a sequence wait on an event preferred? If so, why? The following are code snippets from inside a sequence. 1) Create transaction and engage w/ driver, then wait for event. `uvm_create(req) start_item(req); m_state.wait_on_smthg(); // <--- wait here 2) Wait for event, then proceed m_state.wait_on_smthg(); // <--- wait here `uvm_create(req) start_item(req); In this case, the event being waited for is that data of a certain type is available.
21. SystemVerilog Social Club (SVSC) meetup in Santa Clara. May 12th @7pm

SystemVerilog Social Club (SVSC) meetup in Santa Clara. May 12th @7pm. It looks like we may have a guest star at our SVSC meetup next Tuesday. Cliff Cummings. Bring some good questions/problems. If anyone out there wants to join our very informal group which kicks around small SV and UVM examples, stop by. http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley/events/222163018/
22. uvm sequence

By "best", I believe you mean the "best method for someone who is new to UVM". As someone who has been using UVM for a few years, but is still pretty green with it, here are my thoughts. Avoid the `uvm_do macros until you can comfortably work without them. (And in my case, I still don't use them. In my early UVM days, they just led to a lot of confusion for me, as I looked at examples of the different ways to do things.) I found that sticking with the following got me going when I was floundering in the assorted examples online showing different ways to send sequences. `uvm_create(item) start_item(item); // randomize item and/or assign to it here. finish_item(item); I strongly agree with the following. "The [‘uvm_do] macros also obscure a very simple interface for executing sequences and sequence items. Although 18 in number, they are inflexible and provide a small subset of the possible ways of executing. If none of the [‘uvm_do] macro flavors provide the functionality you need, you will need to learn how to execute sequences without the macros. And once you’ve learned that, you might as well code smartly and avoid them all together. " -from Adam Erickson whitepaper -http://events.dvcon.org/2011/proceedings/papers/09_1.pdf
23. `uvm_*_utils macros useful in virtual class extended from uvm_object?

Does an abstract class (virtual class ....), which extends from uvm_object, benefit from using uvm utility macros (`uvm_component_utils, `uvm_object_utils)? As I understand, `uvm_component_utils and `uvm_object_utils are used to register a class w/ the factory so objects of that class can be overridden. But, because an abstract class cannot be instantiated, it cannot be overridden. Is that assessment correct? Are those utils macros doing smthg else besides allowing for 'overriding' capability? (Although I have looked at them, I know I don't fully understand all they're used for.) thanks, From uvm_object_defines.svh: //------------------------------------------------------------------------------ // // Title: Utility and Field Macros for Components and Objects // // Group: Utility Macros // // The ~utils~ macros define the infrastructure needed to enable the // object/component for correct factory operation. See <`uvm_object_utils> and // <`uvm_component_utils> for details. // // A ~utils~ macro should be used inside ~every~ user-defined class that extends // <uvm_object> directly or indirectly, including <uvm_sequence_item> and // <uvm_component>. // // Below is an example usage of the ~utils~ macro for a user-defined object. // //| class mydata extends uvm_object; //| //| `uvm_object_utils(mydata) //| //| // declare data properties
24. Use objections in uvm phase functions? (or just tasks)

T or F: Objections should not be used in the uvm phases which are functions (i.e. build_phase, connect_phase, check_phase, ...). If True, why?
25. CodingStyle: handle name vs create's string name. To match or not?

CodingStyle: handle name vs create's string name. To match or not to match? What pros, cons, or team rules can you share about whether the string name passed into create should match the handle? i.e. //1) object declared, with handle name m_xyz_agent xyz_agent m_xyz_agent; //2) object created. what-string-name will you pass in to ::create? m_xyz_agent or smthg else? m_xyz_agent = xyz_agent::type_id::create("what-string-name",this); When I first started with uvm, I was tripped up a bunch in situations where I confused the handle and the string. A prime example is in the place of what-string-name below. uvm_config_db#(uvm_object_wrapper)::set(this,"*.what-string-name.asdf.main_phase", "default_sequence",xyz_seq::type_id::get()); When different developers use different styles, it can be a headache. So, besides suggesting 'just be consistent', which I fully agree with, what are your preferences, and why? thanks, Most examples I find have the string name passed to create and the handle match. (Having them differ does help a newbie understand what is going on a bit better, I believe.)
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